2001
DOI: 10.1016/s0167-9317(01)00645-1
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Transient effects in PD SOI NMOSFETs

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Cited by 12 publications
(11 citation statements)
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“…34) The RT is the moment when the SM reaches 50% of its maximum value. 7,35) Figure 6 shows the RT variation of the JLBF 1T-DRAM based on θ fin and memory performances are listed in Table IV. The memory performance changed owing to the θ fin variation, but the RT of the JLBF 1T-DRAM exceeded 64 ms due to the separated structure of body fin and operation region.…”
Section: Device Structure and Simulation Methodsmentioning
confidence: 99%
See 1 more Smart Citation
“…34) The RT is the moment when the SM reaches 50% of its maximum value. 7,35) Figure 6 shows the RT variation of the JLBF 1T-DRAM based on θ fin and memory performances are listed in Table IV. The memory performance changed owing to the θ fin variation, but the RT of the JLBF 1T-DRAM exceeded 64 ms due to the separated structure of body fin and operation region.…”
Section: Device Structure and Simulation Methodsmentioning
confidence: 99%
“…[1][2][3][4][5][6] Generally, the 1T-DRAM is based on a silicon-on-insulator (SOI) structure and operates via the floating-body effect. [7][8][9][10][11][12] However, the SOI wafers are too expensive to be used for the mass production. SOI-like structures can be fabricated using polycrystalline silicon, but its grain boundaries affect the transfer characteristics and memory performance of such structures.…”
Section: Introductionmentioning
confidence: 99%
“…Therefore, the 1T-DRAM cells based on partially depleted (PD) or fully depleted (FD) silicon-on-insulator (SOI) technology have been proposed as alternative candidates for future DRAM application. [2][3][4][5][6][7][8][9][10][11][12] Basically, the 1T-DRAM cells utilize a distinctive floating body effect of SOI wafer, and the neutral body regions of the top silicon channel are able to store the charges. Consequently, additional processes for complicated 3D capacitors of conventional DRAM cell are unnecessary.…”
Section: Introductionmentioning
confidence: 99%
“…Thus, many researchers have been trying to enhance it by accumulating and removing holes in the floating body of a silicon-on-insulator (SOI) wafer. [4][5][6][7][8][9][10][11][12][13] However, although channel doping concentration directly affects the drain current characteristics of the floating body effect in the channel region, no investigations have yet been done on how the doping concentration affects the memory margin of a Cap-less memory cell fabricated on a fully depleted (FD) SOI n-metal-oxide-semiconductor field-effect transistor (n-MOSFET).…”
Section: Introductionmentioning
confidence: 99%