A simple true 1 transistor dynamic random access memory (DRAM) cell concept is proposed for the first time, using the body charging of partially-depleted SOI devices to store the logic "1" or "0" binary states. This cell is two times smaller in area than the conventional 8 2 1T/1C DRAM cell and the process of its manufacturing does not require the storage capacitor fabrication steps. This concept will allow the manufacture of simple low cost DRAM and embedded DRAM chips for 100 and sub-100 nm generations.
Dielectric breakdown of (Pb,La)(Zr,Ti)O3(PLZT) film capacitors with Pt and SrRuO3 electrodes, in its initial or virgin state and after voltage cycling that causes polarization fatigue, is studied by constant-current measurements. It is shown that for different types of PLZT capacitors, the breakdown onset is controlled by the critical charge flown through the film (charge to breakdown) rather than the voltage applied to the capacitor. The charge to breakdown for the asymmetrical Pt/SrRuO3/PLZT/Pt capacitors is found to be much higher that that for the Pt/PLZT/Pt system. Polarization fatigue caused by bipolar voltage cycling provokes a substantial decrease of charge to breakdown. These results can be interpreted in terms of percolation model used for breakdown in SiO2, where the charge to breakdown is associated with injected-carrier-assisted creation of the critical concentration of defects required for formation of the breakdown paths. In this article we propose two possible mechanisms for interpretation of the observed variation of the PLZT capacitor breakdown performance. One mechanism is based on different contributions of PLZT film grains and grain boundaries to the total current flowing through the system. The second mechanism is related to the different kinetics of generation and relaxation of defects in the band gap of the PLZT film. The decrease of the charge to breakdown induced by polarization fatigue is explained by generation of defects during the fatigue bipolar polarization reversals.
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