A capacitor-less 1T-DRAM cell

Abstract

A simple true 1 transistor dynamic random access memory (DRAM) cell concept is proposed for the first time, using the body charging of partially-depleted SOI devices to store the logic "1" or "0" binary states. This cell is two times smaller in area than the conventional 8 2 1T/1C DRAM cell and the process of its manufacturing does not require the storage capacitor fabrication steps. This concept will allow the manufacture of simple low cost DRAM and embedded DRAM chips for 100 and sub-100 nm generations.

Gate-to-Source/Drain Nonoverlap Device for Soft-Program Immune Unified RAM (URAM)

“…Unlike the conventional 1T/1C DRAM, the DRAM mode of URAM uses a floating-body hysteresis effect, which enables the capacitorless 1T-DRAM [3]. Because an O/N/O gate dielectric is used in a partially depleted floating-body structure, the operation of the NVM and capacitorless 1T-DRAM can be realized in a single memory transistor.…”

Mechanisms of charge modulation in the floating body of triple-well nMOSFET capacitor-less DRAMs

“…Capacitor-less DRAMs have recently attracted much attention as very promising scalable ultradense DRAM memories [1][2][3][4][5][6][7], capable to overcome the capacitor integration for the nanoscale memories. Floating body bulk-Si, SOI and doublegate MOSFETs are such candidates but there is need for understanding and modeling the dynamic behavior for these kind of memory devices.…”

Unified Dual-Gate Phase Change RAM (PCRAM) with Phase Change Memory and Capacitor-Less DRAM

“…capacitor-less DRAM이 연구되고 있다 [2]. NVM 는 전기 전도도 (electric conductivity)이고, 는 전류밀도이고, V는 전위 (electric potential)이다.…”