Optimal Channel Ion Implantation for High Memory Margin of Capacitor-Less Memory Cell Fabricated on Fully Depleted Silicon-on-Insulator

Abstract

We study the kinetics of a search of a single fixed target by a large number of searchers performing an intermittent biased random walk in a homogeneous medium. Our searchers carry out their walks in one of two states between which they switch randomly. One of these states (search phase) is a nearest-neighbor walk characterized by the probability of stepping in a given direction (i.e. the walks in this state are not necessarily isotropic). The other (relocation phase) is characterized by the length of the jumps (i.e. when in this state a walker does not perform a nearest-neighbor walk). Within such a framework, we propose a model to describe the searchers' dynamics, generalizing results of our previous work. We have obtained, and numerically evaluated, analytic results for the mean number of distinct sites visited up to a maximum evolution time. We have studied the dependence of this quantity on both the transition probability between the states and the parameters that characterize each state. In addition to our theoretical approach, we have implemented Monte Carlo simulations, finding excellent agreement between the theoretical-numerical and simulations results.

A multi-level capacitor-less memory cell fabricated on a nano-scale strained silicon-on-insulator

“…Optimizing the thickness and doping concentration of the silicon channel in FD SOI n-MOSFETs has been proposed as a way to enhance the memory margin of capacitor-less memory cells [10,11]. Note that the Si channel thickness in FD SOI n-MOSFETs is several tens of nanometers, and a specific thickness and doping concentration in the silicon channel exhibits the maximum memory margin.…”