Traffic- and Thermal-Aware Run-Time Thermal Management Scheme for 3D NoC Systems

Chao, Chia-Ter; Jheng, Kai-Yuan; Wang, Haoyu; Wu, Jiacheng; Wu, An-Yeu

doi:10.1109/nocs.2010.32

Cited by 114 publications

(59 citation statements)

References 11 publications

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“…For communication-centric applications, TL maps the edges with larger communication volumes to vertical links, while for computation-centric applications, TL attempts to map the tiles to the bottom layer. Most DTM methods, like those proposed in [4,[21][22], use dynamic voltage/frequency scaling (DVFS) to control the voltage/frequency of the components so that the temperature can be controlled eventually. However, DVFS requires additional circuits which might incur additional hardware cost.…”

Section: Thermal Management Approaches For 3-d Nocmentioning

confidence: 99%

Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip

Wang

Liu

Yang

et al. 2013

J. Comput. Sci. Technol.

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Abstract3-D Networks-on-Chip (NoC) emerge as a potent solution to address both the interconnection and design complexity problems facing future Multiprocessor System-on-Chips (MPSoCs). Effective run-time mapping on such 3-D NoC-based MPSoCs can be quite challenging, as the arrival order and task graphs of the target applications are typically not known a priori, which can be further complicated by stringent energy requirements for NoC systems. This paper thus presents an energy-aware run-time incremental mapping algorithm (ERIM) for 3-D NoC which can minimize the energy consumption due to the data communications among processor cores, while reducing the fragmentation effect on the incoming applications to be mapped, and simultaneously satisfying the thermal constraints imposed on each incoming application. Specifically, incoming applications are mapped to cuboid tile regions for lower energy consumption of communication and the minimal routing. Fragment tiles due to system fragmentation can be gleaned for better resource utilization. Extensive experiments have been conducted to evaluate the performance of the proposed algorithm ERIM, and the results are compared against the optimal mapping algorithm (branch-and-bound) and two heuristic algorithms (TB and TL). The experiments show that ERIM outperforms TB and TL methods with significant energy saving (more than 10%), much reduced average response time, and improved system utilization.

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Section: Thermal Management Approaches For 3-d Nocmentioning

confidence: 99%

Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip

Wang

Liu

Yang

et al. 2013

J. Comput. Sci. Technol.

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“…• C under high traffic [2]. Such high temperatures result in 4% -10% fault probabilities (bottom subfigure of Figure 6) for a chip that is fault-free in nominal conditions.…”

Section: Fault Probabilities At Runtimementioning

confidence: 99%

Enabling system-level modeling of variation-induced faults in networks-on-chips

Aisopos

Chen

Peh

2011

Proceedings of the 48th Design Automation Conference

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Process Variation (PV) is increasingly threatening the reliability of Networks-on-Chips. Thus, various resilient router designs have been recently proposed and evaluated. However, these evaluations assume random fault distributions, which result in 52%-81% inaccuracy. We propose an accurate circuit-level fault-modeling tool, which can be plugged into any system-level NoC simulator, quantify the system-level impact of PV-induced faults at runtime, pinpoint fault-prone router components that should be protected, and accurately evaluate alternative resilient multi-core designs.

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“…AnYeu Wu and his teammates continuously propose a variety of routing policies [5,6,7,8,9,10,11]. However, those routing algorithms only choose routing path based on local temperature and throughput, and it doesn't consider a solution for the traffic balance problem.…”

Section: Introductionmentioning

confidence: 99%

The Adaptive Thermal and Traffic-Balanced Routing algorithm based on temperature analysis and traffic statistics

Zhou

et al. 2015

IEICE Electron. Express

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Recently, 3D NOC is proposed as an efficient architecture to optimize system performance. However, its die-stacking architecture further results in severe heat and traffic congestion problem. In the view of that, a new Adaptive Thermal and Traffic Balanced ZXY Routing algorithm (ATTBR) is proposed to solve the problems. Experiments has shown that, in the 4 × 4 × 4 3D Mesh, ATTBR has a better throughput and average delay performance achieves 34.67% and 14.85% increment in Temperature-Traffic Balance Product which indicates thermal and traffic balance performance, compared to Regional avoidance routing algorithm and Vertically Downward Routing algorithm.

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Traffic- and Thermal-Aware Run-Time Thermal Management Scheme for 3D NoC Systems

Cited by 114 publications

References 11 publications

Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip

Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip

Enabling system-level modeling of variation-induced faults in networks-on-chips

The Adaptive Thermal and Traffic-Balanced Routing algorithm based on temperature analysis and traffic statistics

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