Enabling system-level modeling of variation-induced faults in networks-on-chips

Aisopos, Konstantinos; Chen, Chia-Hsin Owen; Peh, Li-Shiuan

doi:10.1145/2024724.2024931

Cited by 34 publications

(17 citation statements)

References 20 publications

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“…Thereafter, network operation resumes normally. Ariadne leverages up*/down* routing 3 , a deadlock-free algorithm that can operate on any irregular topology [27]. Up*/down* requires each link to be assigned a direction: up or down.…”

Section: Ariadne Algorithmmentioning

confidence: 99%

“…MOTIVATION Recent studies project that there will be many transistor failures during the lifetime of many-core chips fabricated at advanced technology nodes. Researchers have characterized the impact of technology scaling on device reliability in processors [28] and Networks-on-Chips (NoCs) [3], and indicate that the number of permanent failures is expected to increase. Borkar of Intel expects that at future technology nodes 20% of transistors in chip multiprocessors will be unusable due to variations of the manufacturing process, while an additional 10% of transistors will eventually fail over the lifetime of the chip due to wear-out [7,8].…”

Section: Introductionmentioning

confidence: 99%

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ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment

Aisopos

DeOrio

Peh

et al. 2011

2011 International Conference on Parallel Architectures and Compilation Techniques

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Abstract-Extreme transistor technology scaling is causing increasing concerns in device reliability: the expected lifetime of individual transistors in complex chips is quickly decreasing, and the problem is expected to worsen at future technology nodes. With complex designs increasingly relying on Networks-on-Chip (NoCs) for on-chip data transfers, a NoC must continue to operate even in the face of many transistor failures. Specifically, it must be able to reconfigure and reroute packets around faults to enable continued operation, i.e., generate new routing paths to replace the old ones upon a failure. In addition to these reliability requirements, NoCs must maintain low latency and high throughput at very low area budget.In this work, we propose a distributed reconfiguration solution named Ariadne, targeting large, aggressively scaled, unreliable NoCs. Ariadne utilizes up*/down* for fast routing at high bandwidth, and upon any number of concurrent network failures in any location, it reconfigures to discover new resilient paths to connect the surviving nodes. Experimental results show that Ariadne provides a 40%-140% latency improvement (when subject to 50 faults in a 64-node NoC) over other on-chip state-of-the-art fault tolerant solutions, while meeting the low area budget of on-chip routers with an overhead of just 1.97%.

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Section: Ariadne Algorithmmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment

Aisopos

DeOrio

Peh

et al. 2011

2011 International Conference on Parallel Architectures and Compilation Techniques

Self Cite

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“…System modeling can provide estimates for system parameters, like buffer and queue sizes [11]. As for circuit-52 Ahmed S. Hassan, et al: Clustered Networks-on-Chip: Simulation and Performance evaluation level simulation, technology parameters are taken into consideration, like critical path delays and temperature variation [12]. For early design space exploration, systemlevel simulators are more suitable.…”

Section: Introductionmentioning

confidence: 99%

Clustered Networks-on-Chip: Simulation and Performance Evaluation

Hassan¹

2017

IJCDS

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In many-core Networks-on-Chip (NoC) systems, two topics have recently been researched; NoC clustering and NoC simulation. NoC clustering investigates grouping processing elements (PEs) based on common characteristics between them, like spatial locality or communication patterns. Research showed that NoC clustering achieved better performance and load balancing. Furthermore, it allows scalability of the NoC grid. The other topic, NoC simulation, provides tools for early evaluation of NoC systems. This allowed easy investigation of NoC systems with large number of PEs. Plenty of research has been done in both topics separately. In this paper, we try to fill the gap. We extend an existing NoC simulation tool by adding support for simulating NoC clusters and inter-NoC traffic. The presented NoC clustering simulator supports the modular design technique, which in turn offers the flexibility in configuring cluster parameters. Examples of configurable parameters that are supported by our modified simulator are: adding interconnection topologies to configure how the NoC entities are connected with each other, adding a cluster manager that maps tasks to NoC entities based on the inter-NoC communication pattern, adding latency factors of cluster links in the case of inter-NoC traffic, and adapting the routing algorithm for both inter-cluster and intra-cluster traffic. A clustered NoC simulation case study shows the effectiveness of the modifications made to the simulator. For example, a certain NoC setup is simulated twice, initially non-clustered then clustered, using the added features. Collected data shows that the average clustered NoC routers' energy consumption is 50% lower than the consumption in the non-clustered case.

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“…However, recent work on fault modeling [3] has indicated that NoCs fabricated at advanced technology nodes become increasingly unreliable, causing a number of faults, such as loss or corruption of network messages. In order to mitigate this trend, resilient NoC designs have been proposed to allow correct operation in the face of faults in router hardware [9,12] and links [4,18].…”

Section: Introductionmentioning

confidence: 99%

“…However, no resilient NoC can guarantee 100% reliable data transfers (see Section 6). Thus, a subset of network faults is expected to be exposed to upper layers causing lost coherence messages [3], or corrupted coherence messages that are dropped at the destination node when the packet checksum is recomputed [3,7]. Unfortunately, the loss of a single coherence message can cause the entire system to deadlock.…”

Section: Introductionmentioning

confidence: 99%

A systematic methodology to develop resilient cache coherence protocols

Aisopos

Peh

2011

Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture

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Aggressive transistor scaling continues to increase integration capacity with each new technology node, but technology downscaling also increases the vulnerability of semiconductor devices and causes silicon failures. Thus, fault-tolerant architectures are emerging to guarantee reliable functionality on unreliable silicon. While tolerating faults within a processor core has been extensively researched, the many-core era introduces the challenge of reliable on-chip communication in Chip Multi-Processors (CMPs). In CMP systems, an unreliable interconnection network can lose or corrupt coherence messages, causing the entire chip to deadlock. In this work, we argue for a system-level resiliency solution to tolerate an unreliable underlying Network-on-Chip (NoC). We introduce a systematic methodology to transform a coherence protocol to a resilient one, by extending its Finite State Machine (FSM) with safe states and incorporating additional handshaking messages into transactions. The modified protocol ensures coherent and reliable transactions over any lossy NoC. Our approach is generic and can be applied to a wide range of protocols. It requires minimal hardware modifications and introduces only a slight performance overhead (an average of 0.8% during fault-free operation, and 1.9% even at an aggressive fault rate of one fault per msec).

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Enabling system-level modeling of variation-induced faults in networks-on-chips

Cited by 34 publications

References 20 publications

ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment

ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment

Clustered Networks-on-Chip: Simulation and Performance Evaluation

A systematic methodology to develop resilient cache coherence protocols

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