A systematic methodology to develop resilient cache coherence protocols

Abstract

Aggressive transistor scaling continues to increase integration capacity with each new technology node, but technology downscaling also increases the vulnerability of semiconductor devices and causes silicon failures. Thus, fault-tolerant architectures are emerging to guarantee reliable functionality on unreliable silicon. While tolerating faults within a processor core has been extensively researched, the many-core era introduces the challenge of reliable on-chip communication in Chip Multi-Processors (CMPs). In CMP systems, an unreliable interconnection network can lose or corrupt coherence messages, causing the entire chip to deadlock. In this work, we argue for a system-level resiliency solution to tolerate an unreliable underlying Network-on-Chip (NoC). We introduce a systematic methodology to transform a coherence protocol to a resilient one, by extending its Finite State Machine (FSM) with safe states and incorporating additional handshaking messages into transactions. The modified protocol ensures coherent and reliable transactions over any lossy NoC. Our approach is generic and can be applied to a wide range of protocols. It requires minimal hardware modifications and introduces only a slight performance overhead (an average of 0.8% during fault-free operation, and 1.9% even at an aggressive fault rate of one fault per msec).

Revisiting the Complexity of Hardware Cache Coherence and Some Implications

“…Although some have argued that hardware coherence is here to stay [Martin et al 2012] and continue to work on even more complex extensions [Aisopos and Peh 2011], others are proposing systems that use software-directed coherence [Borkar 2011;Choi et al 2011;Howard et al 2010;IntelSCC 2009;Kelm et al 2009]. This article adds objective results from a concrete case study to this debate.…”

“…There is an ongoing debate about whether we have tamed the complexity of hardware coherence protocols or whether we should abandon them and replace them with their software counterparts. While some predict that hardware cache coherence is here to stay [Martin et al 2012] and continue to extend such protocols in newer, more complex ways [Aisopos and Peh 2011;Zhao et al 2013], others propose and build systems with software-directed coherence [Borkar 2011;Choi et al 2011;Howard et al 2010;IntelSCC 2009;Kelm et al 2009]. Our work offers an objective case study to show that hardware coherence remains quite complex and that a hardware-software co-design approach can provide a simpler alternative.…”

“…A recent position paper makes the case that hardware coherence is here to stay [Martin et al 2012]. Other researchers continue to extend current protocols in new ways that make them even more complex [Aisopos and Peh 2011]. On the other hand, Intel has recently built a 48-core Single-Chip Cloud Computer (SCC) [IntelSCC 2009] that abandons hardware cache coherence, replacing it with software managed caches and their attendant programming complexity.…”

Prism

“…Even though this work assures impeccable soft-error coverage (cf. Table 1), its effectiveness is debatable as it requires intrusive hardware changes to the core-pipeline and private caches for re-execution, and also demands a resilient cache coherence protocol [3] for functional correctness. Additionally, due to the interference effects and moderate soft-error coverage, these works provide low system availability.…”

Toward a Coherent Multicore Memory Model

“…Additionally, Shi and Khan combine their technique with a resilient cache coherence protocol to trade off performance and energy for soft-error coverage. 13 T here are, of course, other challenges in the design and implementation of many-core systems in addition to hardware shared memory-off-chip bandwidth requirements and on-chip power budgets, to name two. Enabling many-core shared memory will go a long way toward easing programmer burden, so the focus can be on application optimization to reduce bandwidth and energy requirements.…”