Trade-offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip

Rijpkema, Edwin; Goossens, Kees; Rădulescu, A.; Dielissen, J.; Meerbergen, J. van; Wielage, Paul; Waterlander, E.

doi:10.1007/978-1-4020-6488-3_10

Cited by 62 publications

(96 citation statements)

References 11 publications

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“…In each arbitration decision, more than one path can be constructed by the crossroad switch as long as no contention exists between these paths. For most existing switch designs, virtual-channel flow-control-based router design, which provides better flexibility and channel utilization with smaller buffer size, is a well-known technique from the domain of multiprocessor networks [17][18][19][20][21][22][23][24].…”

Section: Network Layermentioning

confidence: 99%

“…While in a connection-less network, a nonoptimal priority assignment has less degradation of throughput though it provides coarse QoS support. As pointed out in [20], guaranteed services require resource reservation for the worst case in a connection oriented, which causes a lot of wasted resource. In addition, some quantitative modeling and comparison of these two schemes, provided in [56], has shown that under a variable-bit-rate application, connection-less technique provides a better performance in terms of the end-to-end packet delay.…”

Section: Journal Of Electrical and Computer Engineeringmentioning

confidence: 99%

See 1 more Smart Citation

Networks on Chips: Structure and Design Methodologies

Tsai

Lan

et al. 2012

Journal of Electrical and Computer Engineering

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The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors (CMPs) will contain hundreds or thousands of cores. Such a many-core system requires high-performance interconnections to transfer data among the cores on the chip. Traditional system components interface with the interconnection backbone via a bus interface. This interconnection backbone can be an on-chip bus or multilayer bus architecture. With the advent of many-core architectures, the bus architecture becomes the performance bottleneck of the on-chip interconnection framework. In contrast, network on chip (NoC) becomes a promising on-chip communication infrastructure, which is commonly considered as an aggressive long-term approach for onchip communications. Accordingly, this paper first discusses several common architectures and prevalent techniques that can deal well with the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC. Finally, a novel bidirectional NoC (BiNoC) architecture with a dynamically self-reconfigurable bidirectional channel is proposed to break the conventional performance bottleneck caused by bandwidth restriction in conventional NoCs.

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Section: Network Layermentioning

confidence: 99%

Section: Journal Of Electrical and Computer Engineeringmentioning

confidence: 99%

Networks on Chips: Structure and Design Methodologies

Tsai

Lan

et al. 2012

Journal of Electrical and Computer Engineering

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“…Different from existing VOQ routers [5], [9], SOBR has the following features: (1) output buffered architecture is used, rather than input buffered architecture.…”

Section: Overall Architecturementioning

confidence: 99%

SOBR: A High-Performance Shared Output Buffered Router for Networks-on-Chip

Chen

Xie

2012

IEICE Trans. Inf. & Syst.

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“…Reserved slots traverse the network in a well synchronised manner without having to arbitrate for the output link with the rest of the traffic. The Aethereal NoC developed at Philips and the Sonics on-chip bus employ a TDM technique to support guaranteed throughput [34,35]. Although TDM provides a high level of QoS it is unsuitable for asynchronous implementation because it requires global synchronisation between network elements.…”

Section: Qos For Nocsmentioning

confidence: 99%

Asynchronous on-chip networks

Amde¹,

Felicijan²,

Efthymiou³

et al. 2006

System-on-Chip: Next Generation Electronics

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Various kinds of asynchronous interconnect and synchronisation mechanisms are being proposed for designing low power, low emission and high-speed SOCs. They facilitate modular design and possess greater resilience to fabrication time inter-chip and run-time intra-chip process variability. They can provide a solution for low power consumption in chips and simplify global timing assumptions, e.g. on clock skew, by having asynchronous communication between modules. A few methodologies, including globally asynchronous, locally synchronous and desynchronisation, aim at leveraging the benefits of both synchronous and asynchronous design paradigms. The authors survey various methodologies used for leveraging asynchronous on-chip communication. They investigate various GALS based implementations, desynchronisation strategies and asynchronous network-on-chip (NoC) designs.

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Trade-offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip

Cited by 62 publications

References 11 publications

Networks on Chips: Structure and Design Methodologies

Networks on Chips: Structure and Design Methodologies

SOBR: A High-Performance Shared Output Buffered Router for Networks-on-Chip

Asynchronous on-chip networks

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