Timing Yield Slack for Timing Yield-Constrained Optimization and Its Application to Statistical Leakage Minimization

Hwang, Eun Ju; Kim, Wook; Kim, Young Hwan

doi:10.1109/tvlsi.2012.2220792

Cited by 10 publications

(6 citation statements)

References 29 publications

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“…During each traversing, the average criticality of the gates in fan-out cone of each gate is computed (line [11][12][13][14][15][16][17][18][19][20][21]. If the gate is an output gate (a gate with no predecessor), the average criticality of this gate is equal to its criticality (line [11][12][13][14][15]. The average criticalities of other gates are computed by calculating the average of the criticality of their predecessors (line [16][17][18][19].…”

Section: Merging Arrival Timesmentioning

confidence: 99%

“…Then, each gate is visited in the topological order (line 10). During each traversing, the average criticality of the gates in fan-out cone of each gate is computed (line [11][12][13][14][15][16][17]. The average criticality of each gate is computed by calculating the average of the criticality of the gates in some levels, i.e.…”

Section: Merging Arrival Timesmentioning

confidence: 99%

“…The average criticality of each gate is computed by calculating the average of the criticality of the gates in some levels, i.e. one or two levels, of its fan-out cone (line [11][12][13][14][15]. Finally, using the average criticality of fan-out cone of each gate, the AC of each gate is computed (line 16).…”

Section: Merging Arrival Timesmentioning

confidence: 99%

“…There are many SSTA methods that trade-off between time complexity and accuracy [6][7][8][9][10][11]. Statistical timing optimisation methods take advantages of SSTAs as the basis in order to improve the performance/yield of a digital circuit considering the impacts of process variations [12]. Hence, the efficacy of the statistical timing optimisation method is directly affected by the quality of the SSTAs as well as the information provided by the circuit analyser to be applied in the optimisation method [13].…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Adjacency criticality: a simple yet effective metric for statistical timing yield optimisation of digital integrated circuits

Ebrahimipour

Ghavami

Raji

2019

IET Circuits, Devices & Systems

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As CMOS devices become smaller, process variations-induced uncertainty imposes a large spread in the circuit timing and therefore, it becomes one of the main issues for circuit yield. To analyse/optimise the timing of the circuit under process variation effects, statistical analysis/optimisation techniques are more suitable than the traditional static analysis/ optimisation counterparts. Statistical gate sizing is an effective technique that is widely used to guide the timing yield improvement of digital circuits. Gate criticality, defined as the probability that a gate lies on a critical path, forms the basis for many of the existing statistical gate sizing techniques. Here, the authors introduce adjacency criticality to address the drawbacks of the conventional definition of gate criticality. It is defined as the probability of manufacturing a chip in which the gate lies on the critical path due to process variation considering the effect of the gates in its fan-out cone. Furthermore, the authors present the levelised Adjacency Criticality metric which provides a trade-off between the runtime of the criticality metric and accuracy of the Adjacency Criticality metric. In order to show the efficacy of the proposed metric, an adjacency criticalitybased statistical gate sizing method is presented for improving timing yield of the circuit.

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Section: Merging Arrival Timesmentioning

confidence: 99%

Section: Merging Arrival Timesmentioning

confidence: 99%

Section: Merging Arrival Timesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Adjacency criticality: a simple yet effective metric for statistical timing yield optimisation of digital integrated circuits

Ebrahimipour

Ghavami

Raji

2019

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

show abstract

“…Guthaus et al [20] propose a criticality guided the statistical timing optimization method that sets a criticality threshold for selecting candidate gates. Hwang et al [21] present a way to compute gate swap sensitivity based on direct use of timing yield and yield slack. However, sensitivity based methods may get stuck in the suboptimal points because greedy heuristics only allow the gate with the maximum sensitivity to be replaced [22].…”

Section: Introductionmentioning

confidence: 99%

GenFin: Genetic Algorithm-Based Multiobjective Statistical Logic Circuit Optimization Using Incremental Statistical Analysis

Tang

Jha

2016

IEEE Trans. VLSI Syst.

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As the semiconductor technology node scales into the deep submicrometer regime, it has become very difficult to obtain high IC yields because the process-voltage-temperature variations induce large spreads in delay and power. In this paper, we propose a new framework, called GenFin, which is, as far as we know, the first to target the multiobjective yield optimization of logic circuits. Since FinFETs are a promising substitute for CMOS at 22-nm technology node and beyond, we evaluate the framework with a 22-nm FinFET logic library. By combining the power of genetic algorithm (GA) and adaptive multiobjective optimization, GenFin produces a set of nondominated logic circuits whose timing, leakage power, and dynamic power yields are simultaneously optimized. This can help designers make tradeoff decisions wisely and avoid suboptimal solutions. We also propose an incremental statistical circuit analyzer, called incremental FinPrin, that speeds up the statistical static timing analysis by up to 9.6× and the statistical power analysis by up to 2235.7×, while incurring errors of only up to 0.031% in mean and 0.74% in standard deviation relative to nonincremental analysis. We use heuristics based on the deterministic timing analysis and gate criticality to reduce the GA search space and also improve the quality of its solutions. We present extensive experimental results to demonstrate the efficacy of GenFin. IndexTerms-FinFETs, genetic algorithm (GA), multiobjective optimization, Pareto rank, process-voltagetemperature (PVT) variations, statistical analysis, yield analysis. 1063-8210

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Multivariate Modeling of Variability Supporting Non-Gaussian and Correlated Parameters

Lange

Sohrmann

Jancke

et al. 2016

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Process variations and atomic-level fluctuations increasingly pose challenges to the design and analysis of integrated circuits by introducing variability. Although several approaches have been proposed to deal with the inherent statistical nature of circuit design, we consider them incomplete with two important aspects often being insufficiently addressed: non-Gaussian distributions and highly correlated parameters. To address these points, we propose a fully multivariate and non-Gaussian approach based on an arbitrary model. A subset of the model parameters is treated as a multi-dimensional random variable, which is represented by a combination of generalized lambda distributions and Spearman rank correlation matrices -a very general approach with nearly arbitrary freedom in distribution shapes and parameter correlations. In our application scenarios, we show that such a model is able to fully and accurately capture variability in device compact models and standard cell performance models. Finally, we present adapted analysis methods making use of these models in circuit simulations and in efficient gate level analyses of digital circuits with high accuracy. I. INTRODUCTIONP ROCESS VARIATIONS and atomic-level fluctuations result in integrated circuit (IC) performance variability. To achieve circuits fulfilling their specifications, such effects have to be taken into account during circuit design and analysis [1].Global variations shift the parameters of all devices per die equally. They have always affected ICs and can be tackled by corner-based analysis approaches that assume the most extreme parameter combinations [2]. However, local variations, causing identically designed devices on the same die and in close proximity to randomly differ, have rapidly gained importance since the 90 nm technology node [2]. In combination, global and local variations lead to correlated device variability. Neglecting local variations, corner-based approaches are not sufficient any more. Instead, new modeling and analysis methods are required to adequately analyze the impact of variability during IC design [2]-[4].In Sec. II, the state of the art to handle variability is reviewed for device compact models and digital circuit design. This survey shows that a variety of methods already exists, but most of them focus on particular tasks and often make A. Lange, Ch. Sohrmann, R. Jancke, and J. Haase are with the Fraunhofer Institute for Integrated Circuits (IIS), Design Automation Division (EAS), 01069 Dresden, Germany (email: [andre.lange, christoph.sohrmann, roland.janke, joachim.haase]@eas.iis.fraunhofer.de).

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Timing Yield Slack for Timing Yield-Constrained Optimization and Its Application to Statistical Leakage Minimization

Cited by 10 publications

References 29 publications

Adjacency criticality: a simple yet effective metric for statistical timing yield optimisation of digital integrated circuits

Adjacency criticality: a simple yet effective metric for statistical timing yield optimisation of digital integrated circuits

GenFin: Genetic Algorithm-Based Multiobjective Statistical Logic Circuit Optimization Using Incremental Statistical Analysis

Multivariate Modeling of Variability Supporting Non-Gaussian and Correlated Parameters

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