GenFin: Genetic Algorithm-Based Multiobjective Statistical Logic Circuit Optimization Using Incremental Statistical Analysis

Abstract

As the semiconductor technology node scales into the deep submicrometer regime, it has become very difficult to obtain high IC yields because the process-voltage-temperature variations induce large spreads in delay and power. In this paper, we propose a new framework, called GenFin, which is, as far as we know, the first to target the multiobjective yield optimization of logic circuits. Since FinFETs are a promising substitute for CMOS at 22-nm technology node and beyond, we evaluate the framework with a 22-nm FinFET logic library. By combining the power of genetic algorithm (GA) and adaptive multiobjective optimization, GenFin produces a set of nondominated logic circuits whose timing, leakage power, and dynamic power yields are simultaneously optimized. This can help designers make tradeoff decisions wisely and avoid suboptimal solutions. We also propose an incremental statistical circuit analyzer, called incremental FinPrin, that speeds up the statistical static timing analysis by up to 9.6× and the statistical power analysis by up to 2235.7×, while incurring errors of only up to 0.031% in mean and 0.74% in standard deviation relative to nonincremental analysis. We use heuristics based on the deterministic timing analysis and gate criticality to reduce the GA search space and also improve the quality of its solutions. We present extensive experimental results to demonstrate the efficacy of GenFin. IndexTerms-FinFETs, genetic algorithm (GA), multiobjective optimization, Pareto rank, process-voltagetemperature (PVT) variations, statistical analysis, yield analysis. 1063-8210

Spider monkey optimization–based high‐level synthesis in VLSI circuits for runtime adaptability

“…In the aforementioned graph, 10 different benchmark circuits are considered in “X” axis and the error rate is taken in “Y” axis. From the aforementioned figure, the blue color cone represents the error rate of SSMO‐HLS Model where green color and red color symbolize the error rate of GenFin Technique 1 and FU Power‐Gating Technique 2 . From figure, it is clear that the error rate using SSMO‐HLS Model is comparatively lesser than existing GenFin Technique 1 and FU Power‐Gating Technique 2 …”

“…The ISCAS‐89 benchmark circuits comprises four inputs, one output, three D‐type flipflops, two inverters, and eight gates (one AND + one NAND + two OR + four NOR). SSMO‐HLS model is introduced for fault detection and compared with existing GenFin Technique 1 and FU Power‐Gating Technique 2 . The effectiveness of SSMO‐HLS model is evaluated along with the metrics such as error rate, FU selection accuracy, and circuit adaptability time.…”

“…Table 1 describes the FU selection accuracy of three techniques, namely, GenFin Technique, FU Power‐Gating Technique, and SSMO‐HLS Model. From the table value, it is observed that FU selection accuracy using proposed SSMO‐HLS Model is higher when compared to existing GenFin Technique 1 and FU Power‐Gating Technique 2 . HLS is carried out to transform the behavioral description into the optimized register‐transfer level digital design.…”

“…For multiobjective yield optimization of logic circuits, a new technique termed GenFin was designed in the work of Tang and Jha 1 . GenFin generated collection of non‐dominated logic circuits where timing, leakage power, and dynamic power yields were optimized.…”

Statistical Simulations of Delay Propagation in Large Scale Circuits Using Graph Traversal and Kernel Function Decomposition

“…As technology continues to scale down, the impact of process variations (such as process-voltage-temperature variations) on timing grows (see e.g. [3], [4]). Also variations arise from the manufacturing process (e.g.…”