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As feature sizes shrink, random fluctuations gain importance in semiconductor manufacturing and integrated circuit design. Therefore, statistical device variability has to be considered in circuit design and analysis to properly estimate their impact and avoid expensive over-design. Statistical MOSFET compact modeling is required to accurately capture marginal distributions of varying device parameters and to preserve their statistical correlations. Due to limited simulator capabilities, variables are often assumed to be normally distributed. Although correlations may be captured using Principal Component Analysis, such an assumption may be inaccurate. As an alternative, Nonlinear Power Models have been proposed. Since we see some limitations in this approach, we analyze whether the multivariate Generalized Lambda Distribution is an alternative for statistical device modeling. Applying both approaches to extracted statistical device parameters, we conclude that both methods do not differ significantly in accuracy, but the multivariate Generalized Lambda Distribution is more general and less computationally expensive

Abstract-In this paper a variability-aware compact modeling strategy is presented for 20-nm bulk planar technology, taking into account the critical dimension long-range process variation and local statistical variability. Process and device simulations and statistical simulations for a wide range of combinations of L and W are carefully carried out using a design of experiments approach. The variability aware compact model strategy features a comprehensively extracted nominal model and two groups of selected parameters for extractions of the long-range process variation and statistical variability. The unified variability compact modeling method can provide a simulation frame for variability aware technology circuit co-optimization.

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The degradation of integrated field effect transistors (FETs) is an increasingly critical effect for electronic systems and their product lifetimes. To allow reliability investigations during integrated circuit (IC) design already, multiple electronic design automation (EDA) vendors offer aging simulation capabilities based on SPICE simulations. So far, the bottleneck of aging simulations is the availability of corresponding degradation models that mimick the long-term behavior of FETs due to, for instance, Hot Carrier Injection (HCI) and Bias Temperature Instability (BTI). IC designers need reasonable models that support their particular EDA environment; foundries need to equally support multiple EDA environments to satisfy different customers. To define FET degradation models, subcircuits and model card adaptations are feasible approaches with individual pros and cons. We compare these approaches at example degradation models with identical direct current (DC) behavior. A simulation study with ring oscillators (ROs) shows differences in transient simulation results. By applying subcircuit models, the runtime for simulating the aged circuit worsens by 28 % compared to model card adaptations at a 1000-transistor circuit.

It is well known that random fluctuations in integrated circuit manufacturing introduce variations in circuit performance. While a lot of effort has been spent on circuit variability, fitting performance parameter distributions has not been extensively examined. Our work analyzes whether the Generalized Lambda Distribution suits approximating circuit performance characteristics. We focus on statistical standard cell characterization as an important step towards statistical gate-level and system-level analyses. Our results show that the Generalized Lambda Distribution is not applicable to raw leakage power data. However, timing data and dynamic power consumption may be approximated well. The high characterization effort has to be overcome to achieve industrial application