Comparison of modeling approaches for transistor degradation: model card adaptations vs subcircuits

Abstract

The degradation of integrated field effect transistors (FETs) is an increasingly critical effect for electronic systems and their product lifetimes. To allow reliability investigations during integrated circuit (IC) design already, multiple electronic design automation (EDA) vendors offer aging simulation capabilities based on SPICE simulations. So far, the bottleneck of aging simulations is the availability of corresponding degradation models that mimick the long-term behavior of FETs due to, for instance, Hot Carrier Injection (HCI) and Bias Temperature Instability (BTI). IC designers need reasonable models that support their particular EDA environment; foundries need to equally support multiple EDA environments to satisfy different customers. To define FET degradation models, subcircuits and model card adaptations are feasible approaches with individual pros and cons. We compare these approaches at example degradation models with identical direct current (DC) behavior. A simulation study with ring oscillators (ROs) shows differences in transient simulation results. By applying subcircuit models, the runtime for simulating the aged circuit worsens by 28 % compared to model card adaptations at a 1000-transistor circuit.

On the use of an RTN simulator to explore the quality trade-offs of a novel RTN-based PUF

“…This is carried out stochastically: two identical transistors may feature different RTN events. To carry out the RTN simulation, there are two possible approaches to do so [13]: to incorporate such variations into the transistor model, or to add a controlled voltage source to each gate to account for the threshold voltage shift. Both approaches have benefits and downsides, but the RTN mathematical framework developed can be used either way.…”

RF small-signal modeling of HCI degradation in FDSOI NMOSFET using BSIM-IMG

“…Finally, a second simulation with the degraded devices is performed, and its behavior compared to simulations of fresh devices. The degraded transistor can be modeled with a subcircuit approach that uses voltage and current sources around an unaltered device to mimic the degraded behavior or with a model card approach, where transistor degradation is modeled by drifting parameters of the intrinsic model card [6]. A third possibility is to extend the compact model of the transistor to account for aging effects.…”

“…The use of parasitic resistances has been proposed to model the observed effects of HCI on RF small-signal performance [5], [10]. Adding passive elements in the netlist to model the aging degradation brings difficulties in the integration of the model into the PDK and the extra nodes can affect simulation performance [6]. The BSIM-IMG compact model allows the definition of an extension resistance RD, which can be connected between the external and the internal drain nodes of the transistor, making improvements in RF simulations possible without adding passive elements [10].…”

Challenges and solution approaches for simulation-based reliability assessment – degradation modeling

“…2(a). The subcircuit approach causes losses in simulation performance due to additional nodes and branches [6].…”