Time interleaved C-2C SAR ADC with background timing skew calibration in 65nm CMOS

Abstract

This paper presents a 5GS/s 8-bit 40-way timeinterleaved SAR ADC fabricated in 65nm CMOS. Two-level hierarchical interleaving is employed, resulting in 4 sub-ADCs each operating at 1.25GS/s at the topmost level with front-end track and hold samplers. The sub-ADCs use capacitive C-2C DACs to minimize the input capacitance and area. A novel background timing skew calibration method is used which requires no redundant signal paths. After calibration, the ADC achieves an SNDR of 33.3dB at Nyquist and consumes 138.6mW from a 1V supply with a 5GS/s sampling rate, yielding an FOM of 738fJ/conv-step. The individual sub-ADC achieves an SNDR of 37.9dB at Nyquist and consumes 34.2mW, yielding an FOM of 428fJ/conv-step.

A low-complexity correlation-based time skew estimation technique for time-interleaved SAR ADCs

“…In general, a calibration technique is composed of two processes, estimation and correction. The focus of this paper is the problem of accurate time skew estimation under the assumption that the correction can be done either by analog delay lines, e.g., [2][3][4] or by digital interpolation filters, e.g., [5] and [6].…”

A High-Precision Time Skew Estimation and Correction Technique for Time-Interleaved ADCs

“…The estimated values are plotted with and without the proposed HW simplifications in Section VII and the . 2 approximation in (15). Without these simplifications, ∆ 1 is estimated correctly for small values of ∆ 1 ; however, it suffers from visible non-linearity at large ∆ 1 , this effect is neutralized on convergence as ∆ 1 → 0.…”

“…A. Estimation of the derivative of the autocorrelation function Many calibration algorithms (e.g., those proposed in [4], [15]) ignore the estimation of the term dRxx(Ts) dτ , assuming only that this term is always negative, which is correct for a band-limited input; hence, this term does not affect the adaptation direction of the estimation process. However, it makes the convergence speed dependent on the input signal.…”

“…Figure 2 shows a block diagram of the proposed time skew estimation. It consists of M + 1 correlators; the first M of these are used to compute e using (6) and (10), and the M th correlator is used in estimating T s dRxx(Ts) dτ according to (15). All e are processed jointly to estimate the time skew residues ∆ via (16).…”

“…Many estimation algorithms, e.g., [2]- [4], [11], [14], [15], [17]- [20], choose the first sub-ADC as a timing reference, i.e., r = τ 0 , which, recalling (5), results in the following variance…”