This paper presents a technique to estimate the time skew in time-interleaved ADCs. The proposed method estimates all of the time skew parameters jointly based on observations from a bank of correlators. The proposed method works for an arbitrary number of sub-ADCs. For implementation of the correlator bank, we propose the use of Mitchell's logarithmic multiplier and a hardware reuse mechanism, thereby reducing the complexity and power consumption. Also, we explain why blind estimation techniques alone (including the proposed one) are not always sufficient for time skew estimation for certain classes of input signal; for the proposed approach, however, a simple modification to the analogue circuit (suitable for SAR ADCs) is shown to successfully deal with such problems, with only a minor penalty in power and area. The technique is verified by extensive simulations including a spectrally rich input signal in which an MTPR (multi-tone power ratio) improvement from 29dB to 62dB was achieved for a TIADC system having 16 sub-ADCs.

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This paper presents a generic foreground calibration algorithm which compensates for memoryless nonlinear impairments in pipeline, SAR or hybrid ADC architectures. Amplifier nonlinearity, comparator offsets, capacitance mismatch and settling time errors are considered. During the calibration process, each element of a look up table is computed by mapping each raw ADC output value to an estimate of the corresponding input, and the most likely input corresponding to each raw ADC output is computed and stored in the table; this table is then used during normal operation to map the raw values to the calibrated ADC outputs. Complexity reduction techniques are presented to facilitate an in-circuit hardware implementation in order to reduce foreground calibration time. The algorithm's performance is evaluated using a SAR ADC model suffering from various nonlinear impairments. Results are presented for settling time errors, capacitor mismatch scenarios, and a wide range of nonlinear amplifier parameters, demonstrating a significant performance improvement in all cases.

This paper presents an all-digital background blind calibration technique for the capacitor mismatch problem in SAR ADCs. It utilizes the redundancy offered using a sub-radix-2 DAC architecture to blindly estimate the mismatch and the assigned weight for each comparator decision. The weights are estimated by building partial histogram windows for the comparator decision vectors. To remove the dependency on the input signal's probability density function, the histogram windows are normalized with respect to their peaks. Matlab simulation results show that an ENOB within 0.12bit of the optimal is attained using the proposed algorithm. Index terms-SAR ADC, capacitor mismatch, calibration. I.

This paper presents a generic foreground calibration algorithm which estimates and corrects memoryless nonlinear impairments in both single channel and time-interleaved analog-todigital converters (TIADCs), and which is capable of correcting for amplifier nonlinearity, comparator offsets and capacitance mismatch for each channel. It operates by generating, and then using, a Look-Up Table which maps raw ADC output decision vectors to linearised output. For TIADCs, the algorithm also uses information gained during the calibration phase to estimate timing and gain mismatches among the sub-ADCs. The problem of selecting an appropriate timing reference so as to relax the requirements on the time skew correction circuitry is statistically analysed, as is the corresponding impact on manufacturing yield. Accordingly, a new method is proposed having superior performance; for example, in the case of an 8 sub-ADC TIADC system, the proposed scheme reduces the time skew correction requirement by 44% compared to conventional methods. The architecture is instrumented with some additional circuitry to facilitate built-in self-test (BIST), allowing manufacturing test time and cost reductions. Implementation aspects are discussed, and several complexity reduction techniques are presented along with synthesis results from a Verilog implementation of the calibration engine.

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