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This paper presents a technique to estimate the time skew in time-interleaved ADCs. The proposed method estimates all of the time skew parameters jointly based on observations from a bank of correlators. The proposed method works for an arbitrary number of sub-ADCs. For implementation of the correlator bank, we propose the use of Mitchell's logarithmic multiplier and a hardware reuse mechanism, thereby reducing the complexity and power consumption. Also, we explain why blind estimation techniques alone (including the proposed one) are not always sufficient for time skew estimation for certain classes of input signal; for the proposed approach, however, a simple modification to the analogue circuit (suitable for SAR ADCs) is shown to successfully deal with such problems, with only a minor penalty in power and area. The technique is verified by extensive simulations including a spectrally rich input signal in which an MTPR (multi-tone power ratio) improvement from 29dB to 62dB was achieved for a TIADC system having 16 sub-ADCs.

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In this paper, we propose a lightweight neural network for real-time electrocardiogram (ECG) anomaly detection and system level power reduction of wearable Internet of Things (IoT) Edge sensors. The proposed network utilizes a novel hybrid architecture consisting of Long Short Term Memory (LSTM) cells and Multi-Layer Perceptrons (MLP). The LSTM block takes a sequence of coefficients representing the morphology of ECG beats while the MLP input layer is fed with features derived from instantaneous heart rate. Simultaneous training of the blocks pushes the overall network to learn distinct features complementing each other for making decisions. The network was evaluated in terms of accuracy, computational complexity, and power consumption using data from the MIT-BIH arrhythmia database. To address the class imbalance in the dataset, we augmented the dataset using SMOTE algorithm for network training. The network achieved an average classification accuracy of 97% across several records in the database. Further, the network was mapped to a fixed point model, retrained in a bit accurate fixed-point environment to compensate for the quantization error, and ported to an ARM Cortex M4 based embedded platform. In laboratory testing, the overall system was successfully demonstrated, and a significant saving of ≃50% power was achieved by gating the wireless transmission using the classifier. Wireless transmission was enabled only to transmit the beats deemed anomalous by the classifier. The proposed technique compares favourably with current methods in terms of computational complexity and has the advantage of standalone operation in the edge node, without the need for always-on wireless connectivity making it ideal for IoT wearable devices.

This paper presents a generic foreground calibration algorithm which compensates for memoryless nonlinear impairments in pipeline, SAR or hybrid ADC architectures. Amplifier nonlinearity, comparator offsets, capacitance mismatch and settling time errors are considered. During the calibration process, each element of a look up table is computed by mapping each raw ADC output value to an estimate of the corresponding input, and the most likely input corresponding to each raw ADC output is computed and stored in the table; this table is then used during normal operation to map the raw values to the calibrated ADC outputs. Complexity reduction techniques are presented to facilitate an in-circuit hardware implementation in order to reduce foreground calibration time. The algorithm's performance is evaluated using a SAR ADC model suffering from various nonlinear impairments. Results are presented for settling time errors, capacitor mismatch scenarios, and a wide range of nonlinear amplifier parameters, demonstrating a significant performance improvement in all cases.

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