Threshold voltage tuning by metal gate work function modulation for 10 nm CMOS integration and beyond

Yoshida, N.; Han, Ke; Hsu, P.F.; Beach, Matthew; Lu, X.; Hung, R.; Mao, Daxin; Chen, Hao; Tang, Wenlong; Lei, Yu; Zhou, Jing; Noori, Atif; Jin, Miao; Xu, Kun; Phatak, Anup; Sun, Shiyu; Hassan, Sajjad; Gandikota, Srinivas; Chang, Chorng‐Ping; Brand, A.

doi:10.1109/vlsi-tsa.2014.6839647

Cited by 11 publications

(4 citation statements)

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“…Due to the high interfacial quality of BN dielectrics, the extrinsic doping effect from dielectrics to channels is minimized and, thus, the 6L MoS 2 channel is nearly neutral with a threshold voltage (V t ) around −1V at 300 K. For practical applications, this small V t deviation is expected to be readily tuned through various engineering strategies, such as modulation of the work function of metal gates. 15 Remarkably, the curves show negligible scanning hystereses in the full-range plot, and they become discernible only in the enlarged plots over a 10 mV range, as shown in the insets of Figure 2a. Their values are almost independent with T from 300 to 7.5 K, with an average value of 2 mV, as summarized in the inset of Figure 2b.…”

Section: ■ Results and Discussionmentioning

confidence: 88%

Clean BN-Encapsulated 2D FETs with Lithography-Compatible Contacts

Liang

Wang

Zhou

et al. 2022

ACS Appl. Mater. Interfaces

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Device passivation through ultraclean hexagonal BN encapsulation has proven to be one of the most effective ways of constructing high-quality devices with atomically thin semiconductors that preserve the ultraclean interface quality and intrinsic charge transport behavior. However, it remains challenging to integrate lithography-compatible contact electrodes with flexible distributions and patterns. Here, we report the feasibility of a straightforward integration of lithography-defined contacts into BN-encapsulated two-dimensional field-effect transistors (2D FETs), giving rise to overall device quality comparable to the state-of-the-art results from the painstaking pure dry transfer processing. The electronic characterization of FETs consisting of WSe 2 and MoS 2 channels reveals an extremely low scanning hysteresis of ∼2 mV on average, a low density of interfacial charged impurities of ∼10 11 cm −2 , and generally high charge mobilities over 1000 cm 2 V −1 s −1 at low temperatures. The overall high device qualities verify the viability of directly integrating lithography-defined contacts into BNencapsulated devices to exploit their intrinsic charge transport properties for advanced electronics.

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Section: ■ Results and Discussionmentioning

confidence: 88%

Clean BN-Encapsulated 2D FETs with Lithography-Compatible Contacts

Liang

Wang

Zhou

et al. 2022

ACS Appl. Mater. Interfaces

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“…According to literature, the addition of AlN in TiN can convert pMOSFET to nMOSFET (~4.59 eV) [30]. The composition of TiAl as nWFM can modulate WFM by combining TiN [9]. Figs.…”

Section: A Gate Stacks Of Multi-threshold Voltage Mosfetmentioning

confidence: 98%

“…An undoped or low-doped channel is commonly adopted for advanced devices to avoid this uncertainty. Therefore the WFM gate was introduced as a solution to modulate V t in FinFET devices [7][8][9][10][11][12][13][14][15][16].…”

Section: Introductionmentioning

confidence: 99%

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Modifying Threshold Voltages to n- and p- Type FinFETs by Work Function Metal Stacks

Chang¹,

Li²,

Hsu³

et al. 2021

IEEE Open J. Nanotechnol.

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High-k metal gate technology improves the performance and reduces the gate leakage current of metal-oxide-semiconductor field-effect transistors (MOSFETs). This study investigated four different work function metal (WFM) stacks in the gate of fin field-effect transistors (FinFETs) on the same substrate. These devices not only successfully produced distinct levels of threshold voltages (|V t |) but also converted n-to p-type features merely by adding p-type WFM in the gate of the MOSFETs. All of the devices satisfied short-channel effects with shrinking channel length. The gate-to-body electric field induced drain leakage due to the nature of bulk FinFETs. However, the n-and p-type gate stacks presented different gate current leakage. For reliability, hot carrier injection (HCI) could have a higher reliability impact than the negative-bias temperature instability (NBTI) for p-MOSFET, although the stress voltage of HCI was roughly half that of the NBTI test. This multi-threshold voltage tuning allows designers to design CMOS and choose the trade-off between low power consumption and high performance on the same platform.

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