Modifying Threshold Voltages to n- and p- Type FinFETs by Work Function Metal Stacks

Chang, Wen-Teng; Li, Meng-His; Hsu, Chun-Hao; Lin, Wen-Chin; Yeh, Wen–Kuan

doi:10.1109/ojnano.2021.3109897

Cited by 7 publications

(4 citation statements)

References 38 publications

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“…They are symmetric around −0.3 V in terms of I ON , SS , and drain-induced barrier lowering. The performance symmetry can be adjusted to 0 V by a proper choice of gate metals with appropriate work functions, as typically done in Si CMOS inverters 47 , 48 . The voltage transfer characteristics of the inverter for supply voltage, V DD , varying from 0.2 V to 1 V, show a very decent transition at around −0.3 V + V DD /2.…”

Section: Resultsmentioning

confidence: 99%

Vertical GeSn nanowire MOSFETs for CMOS beyond silicon

et al. 2023

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The continued downscaling of silicon CMOS technology presents challenges for achieving the required low power consumption. While high mobility channel materials hold promise for improved device performance at low power levels, a material system which enables both high mobility n-FETs and p-FETs, that is compatible with Si technology and can be readily integrated into existing fabrication lines is required. Here, we present high performance, vertical nanowire gate-all-around FETs based on the GeSn-material system grown on Si. While the p-FET transconductance is increased to 850 µS/µm by exploiting the small band gap of GeSn as source yielding high injection velocities, the mobility in n-FETs is increased 2.5-fold compared to a Ge reference device, by using GeSn as channel material. The potential of the material system for a future beyond Si CMOS logic and quantum computing applications is demonstrated via a GeSn inverter and steep switching at cryogenic temperatures, respectively.

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Section: Resultsmentioning

confidence: 99%

Vertical GeSn nanowire MOSFETs for CMOS beyond silicon

et al. 2023

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“…Equation (3) [ 87 ] explains V th variations through the FinFET geometrical parameters, where A is the material-dependent parameter, while

and

represent oxide thickness and permittivity, respectively. W and L denote the FinFET width and gate length, respectively.…”

Section: Finfet 6t-sram Cellmentioning

confidence: 99%

“…Moreover, any single fin in the FinFET structure ( Figure 8 ) shows different V th voltages at the center and corner. The difference in the gate work function at these locations is held accountable for this phenomenon [ 87 ].…”

Section: Finfet 6t-sram Cellmentioning

confidence: 99%

FinFET 6T-SRAM All-Digital Compute-in-Memory for Artificial Intelligence Applications: An Overview and Analysis

Gul,

Shams,

Al-Khalili

2023

Micromachines

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Artificial intelligence (AI) has revolutionized present-day life through automation and independent decision-making capabilities. For AI hardware implementations, the 6T-SRAM cell is a suitable candidate due to its performance edge over its counterparts. However, modern AI hardware such as neural networks (NNs) access off-chip data quite often, degrading the overall system performance. Compute-in-memory (CIM) reduces off-chip data access transactions. One CIM approach is based on the mixed-signal domain, but it suffers from limited bit precision and signal margin issues. An alternate emerging approach uses the all-digital signal domain that provides better signal margins and bit precision; however, it will be at the expense of hardware overhead. We have analyzed digital signal domain CIM silicon-verified 6T-SRAM CIM solutions, after classifying them as SRAM-based accelerators, i.e., near-memory computing (NMC), and custom SRAM-based CIM, i.e., in-memory-computing (IMC). We have focused on multiply and accumulate (MAC) as the most frequent operation in convolution neural networks (CNNs) and compared state-of-the-art implementations. Neural networks with low weight precision, i.e., <12b, show lower accuracy but higher power efficiency. An input precision of 8b achieves implementation requirements. The maximum performance reported is 7.49 TOPS at 330 MHz, while custom SRAM-based performance has shown a maximum of 5.6 GOPS at 100 MHz. The second part of this article analyzes the FinFET 6T-SRAM as one of the critical components in determining overall performance of an AI computing system. We have investigated the FinFET 6T-SRAM cell performance and limitations as dictated by the FinFET technology-specific parameters, such as sizing, threshold voltage (Vth), supply voltage (VDD), and process and environmental variations. The HD FinFET 6T-SRAM cell shows 32% lower read access time and 1.09 times better leakage power as compared with the HC cell configuration. The minimum achievable supply voltage is 600 mV without utilization of any read- or write-assist scheme for all cell configurations, while temperature variations show noise margin deviation of up to 22% of the nominal values.

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“…Introducing the intermediate energy level (Mid-Gap) metals such as titanium nitride (TiN, pWFM) or aluminum tantalum (TiAl, nWFM) which modulates the work function of the metal gate. [14][15][16] This material suppresses the gate leakage current while improving the device's characteristics. However, high dielectric constant materials and metal gates are also accompanied by higher interface density, charge trapping (interface/oxide trapped charge (Q it , Q ot ), Mobile ion charge (Q m ) and fixed charge (Q f ), charge trapping/detrapping, low drift rate (low mobility) and other disadvantages.…”

mentioning

confidence: 99%

Hot Carrier Injection Reliability of Fabricated N- and P-Type Multi FinFETs with Different TiN Stacks

Chen

Yeh²,

Hsu³

et al. 2023

ECS J. Solid State Sci. Technol.

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Device degradation due to hot carrier injection (HCI) in multi-fin 20 nm and 10 nm N- and P-type FinFET devices are thoroughly analyzed. To further understand the HCI reliability of the four FinFET devices, the device is fabricated with a standard Vt base and low Vt base gate stacks with different work functions. It is evident that: (i) The standard Vt device sustains lower effective stress bias due to the difference in threshold voltage, resulting in a more stable threshold voltage than the low Vt base device, and (ii) the transconductance of the single N- and P-type FinFET is more severely degraded than the multi-fin N- and P-type FinFET, mainly because multi N- and P-type Finfet has coupe effect, which effectively reduces the impact of HCI

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Modifying Threshold Voltages to n- and p- Type FinFETs by Work Function Metal Stacks

Cited by 7 publications

References 38 publications

Vertical GeSn nanowire MOSFETs for CMOS beyond silicon

Vertical GeSn nanowire MOSFETs for CMOS beyond silicon

FinFET 6T-SRAM All-Digital Compute-in-Memory for Artificial Intelligence Applications: An Overview and Analysis

Hot Carrier Injection Reliability of Fabricated N- and P-Type Multi FinFETs with Different TiN Stacks

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