Vertical GeSn nanowire MOSFETs for CMOS beyond silicon

Abstract

The continued downscaling of silicon CMOS technology presents challenges for achieving the required low power consumption. While high mobility channel materials hold promise for improved device performance at low power levels, a material system which enables both high mobility n-FETs and p-FETs, that is compatible with Si technology and can be readily integrated into existing fabrication lines is required. Here, we present high performance, vertical nanowire gate-all-around FETs based on the GeSn-material system grown on Si. While the p-FET transconductance is increased to 850 µS/µm by exploiting the small band gap of GeSn as source yielding high injection velocities, the mobility in n-FETs is increased 2.5-fold compared to a Ge reference device, by using GeSn as channel material. The potential of the material system for a future beyond Si CMOS logic and quantum computing applications is demonstrated via a GeSn inverter and steep switching at cryogenic temperatures, respectively.

Isothermal Heteroepitaxy of Ge1–xSnx Structures for Electronic and Photonic Applications

“…Note that the Ge 0.85 Sn 0.15 top layer, at p GeH4 = 300 Pa, is epitaxially grown on Ge 0.88 Sn 0.12 , while Sn segregation appears by direct growth on Ge buffer under similar growth conditions (empty pink symbol in Figure a). Structure I design is an upgraded heterostructure for vertical MOSFET devices and CMOS invertors, as recently experimentally demonstrated by Liu et al , The patterning into nanowires (NWs) with diameters below 100 nm results in elastic strain relaxation, offering direct band gap Ge 1– x Sn x semiconductors with a large separation between the Γ- and L-valleys. NW MOSFET devices, as sketched in Figure b, fully benefit from the high mobility of Γ-electrons in direct band gap Ge 1– x Sn x compared to that of L-electrons in the indirect Ge semiconductor, boosting the n-type MOSFET devices.…”

High-κ Gate Dielectric on Tunable Tensile Strained Germanium Heterogeneously Integrated on Silicon: Role of Strain, Process, and Interface States

“…As the industry is adopting high mobility Ge and SiGe channel materials, − and ε-Ge has recently been experimentally reported to increase the carrier mobility than unstrained Ge, alternate measurement method to independently confirm strain in Ge is important for scientific research as well as for technological considerations. The strain relaxation values were further substantiated via Raman spectroscopy.…”

“…Group IV based materials, germanium (Ge), silicon–germanium (SiGe), and germanium–tin (GeSn), are under consideration for nanoelectronics and photonics. − Due to their high carrier mobilities, supplementing these materials along with tunable compositional In x Ga 1– x As (0.1 ≤ x ≤ 0.4) as channel materials will boost the on-current and ultimately device/circuit performance in an alternate channel CMOS, , tensile-strained Ge/In x Ga 1– x As based tunnel transistors, , energy-efficient SRAM cell architecture for ultralow voltage applications, and photonic devices. ,,, For high-performance ultralow voltage CMOS logic, RF circuits, and mixed signal low-noise amplifier circuits, it is widely accepted that InGaAs and Ge will serve as n -channel and p -channel transistor materials, respectively. ,− However, implementing these two different materials (i.e., Ge and InGaAs) on a Si wafer requires defect-controlled buffer engineering for the monolithic heterogeneous integration process rather than direct growth of Ge or SiGe on Si. Furthermore, Ge is an excellent choice for CMOS logic due to its 2.8× and 4.2× higher electron and hole mobilities, respectively, compared to Si.…”

Research progress of out-of-plane GeSn nanowires

“…Currently, the application of out-of-plane GeSn NWs is still in the phase of basic research and technology development. However, the literature indicates that out-of-plane GeSn NWs have many potential applications, especially as infrared photodetectors [55,62,91,159,162,[166][167][168], high-efficiency Li-ion battery anodes [122], nanowire SWIR lasers [152,169,170], nanowire transistors (figure 8) [55,60,61,[171][172][173][174][175].…”

“…Emmanuele Galluccio et al reported for the first time some of the key electronic FET performance metrics of nominally undoped, VLS-grown Ge 1-x Sn x such as mobility, I ON /I OFF ratio, subthreshold swing and transconductance (gm) as a function of Sn content (x = 0.03, 0.06 and 0.09) [171]. Recently, Liu's team proposed vertical GeSn-based GAA NW MOSFETs (VFETs) with NW diameters as small as 25 nm and designed two epitaxial heterostructures, GeSn/ Ge/Si and Ge/GeSn/Si, for the p-and n-VFETs for joint optimization [174]. A schematic of an all-GeSn n-VFET with source/drain is shown in figure 12 reference device, while the transconductance of the p-FET is increased to 850 μS μm −1 by utilising the tiny bandgap of the GeSn as a source, which results in high injection speeds.…”