Clean BN-Encapsulated 2D FETs with Lithography-Compatible Contacts

Abstract

Device passivation through ultraclean hexagonal BN encapsulation has proven to be one of the most effective ways of constructing high-quality devices with atomically thin semiconductors that preserve the ultraclean interface quality and intrinsic charge transport behavior. However, it remains challenging to integrate lithography-compatible contact electrodes with flexible distributions and patterns. Here, we report the feasibility of a straightforward integration of lithography-defined contacts into BN-encapsulated two-dimensional field-effect transistors (2D FETs), giving rise to overall device quality comparable to the state-of-the-art results from the painstaking pure dry transfer processing. The electronic characterization of FETs consisting of WSe 2 and MoS 2 channels reveals an extremely low scanning hysteresis of ∼2 mV on average, a low density of interfacial charged impurities of ∼10 11 cm −2 , and generally high charge mobilities over 1000 cm 2 V −1 s −1 at low temperatures. The overall high device qualities verify the viability of directly integrating lithography-defined contacts into BNencapsulated devices to exploit their intrinsic charge transport properties for advanced electronics.

Enhancement of Carrier Mobility in Semiconductor Nanostructures by Carrier Distribution Engineering

“…In case of BN dielectric (Figure 5a), the component of SO phonons is neglected because it is too weak to be considered. [22,41] The CI densities (nCI) at the bottom and top interfaces are assumed to be identical with nCI = 2 ×10 11 cm −2 for BN [42] and 10 12 cm −2 for HfO2, respectively. The densities of defects (nDF) are assumed to be 10 13 cm −2 at both channel surfaces.…”

Induced Chemical Networking of Organometallic Tin in a Cyclic Framework for Sub-10 nm Patterning and Interconnect Application

“…Reduction in the transistor size in advanced electronic devices is highly essential in view of the current demand of the semiconductor market. , In this regard, nanolithography has been proven to be an indispensable technique for high-volume production of nanochips. − It plays an important role in advancing next-generation integrated circuit (IC) chip fabrication. Recent chip fabrication technology is progressing toward the fabrication of 5 nm node or below with the help of extreme ultraviolet lithography (EUVL) .…”

A graphene/Janus B2P6 heterostructure with a controllable Schottky barrier via interlayer distance and electric field

“…[1][2][3][4][5][6] However, the frequent formation of contact resistance at metal/semiconductor interfaces hinders the injection efficiency of carriers in FETs, which severely restricts the performance of 2D devices. [7][8][9][10][11] Several ways are found to lower the Schottky barrier, such as defects, 12 doping 13 and picking an appropriate semiconductor channel material 14 or metal electrode. 15 Among these, graphene (GR) as a metal electrode is widely applied in FETs.…”