Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded  DRAM Technology

Batra, Pooja; Skordas, Spyridon; LaTulipe, D.; Winstel, Kevin; Kothandaraman, C.; Himmel, Ben; Maier, Gary; He, Bishan; Gamage, Deepal Wehella; Golz, John; Lin, Wei; Vo, Tuan; Priyadarshini, Deepika; Hubbard, Alex; Cauffman, Kristian; Peethala, B.; Barth, J.; Kirihata, T.; Graves-Abe, Troy; Robson, N.; Iyer, Subramanian S.

doi:10.3390/jlpea4020077

Cited by 17 publications

(4 citation statements)

References 16 publications

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“…On the other hand, oxide-oxide direct bonding is a promising candidate for ultra fine-pitch interconnect formation without metal/metal bonding including microbumps [ 22 , 23 ]. Using the direct bonding technologies, wafers or KGDs can be tightly bonded to the corresponding target wafers without adhesives or underfill resins.…”

Section: Introductionmentioning

confidence: 99%

Oxide-Oxide Thermocompression Direct Bonding Technologies with Capillary Self-Assembly for Multichip-to-Wafer Heterogeneous 3D System Integration

et al. 2016

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Plasma- and water-assisted oxide-oxide thermocompression direct bonding for a self-assembly based multichip-to-wafer (MCtW) 3D integration approach was demonstrated. The bonding yields and bonding strengths of the self-assembled chips obtained by the MCtW direct bonding technology were evaluated. In this study, chemical mechanical polish (CMP)-treated oxide formed by plasma-enhanced chemical vapor deposition (PE-CVD) as a MCtW bonding interface was mainly employed, and in addition, wafer-to-wafer thermocompression direct bonding was also used for comparison. N2 or Ar plasmas were utilized for the surface activation. After plasma activation and the subsequent supplying of water as a self-assembly mediate, the chips with the PE-CVD oxide layer were driven by the liquid surface tension and precisely aligned on the host wafers, and subsequently, they were tightly bonded to the wafers through the MCtW oxide-oxide direct bonding technology. Finally, a mechanism of oxide-oxide direct bonding to support the previous models was discussed using an atmospheric pressure ionization mass spectrometer (APIMS).

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Section: Introductionmentioning

confidence: 99%

Oxide-Oxide Thermocompression Direct Bonding Technologies with Capillary Self-Assembly for Multichip-to-Wafer Heterogeneous 3D System Integration

et al. 2016

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“…TSVs provide the shortest vertical interconnections and have a large number of significant advantages, such as higher density, lower energy consumption, wider bandwidth, higher electrical performance, and smaller form factor [5]. Due to its excellent performance, Cu-TSV 3D integration has a broad application in micro-devices [5,8,9]. In order to enhance the reliability and the response speed of microelectronics, copper is selected to replace aluminum and tungsten as the interconnect material and via filling material for printed circuit boards (PCBs) and integrated circuit chips due to its long electromigration lifetimes, high reliability, low electrical resistance, cost effectiveness and good compatibility with integrated circuit modules [8,10].…”

Section: Introductionmentioning

confidence: 99%

Optimization of innovative approaches to the shortening of filling times in 3D integrated through-silicon vias (TSVs)

Zhang

Ding

Wang

et al. 2015

J. Micromech. Microeng.

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The continuously decreasing size of integrated circuits is the driving force for the emergence of three-dimensional (3D) integration. The through-silicon via (TSV) is the heart of 3D IC/Si integrations, providing the shortest vertical interconnections, and it has a large number of significant advantages. In this paper, a new additive system specifically developed for high aspect ratio TSVs is introduced for TSV electroplating. A wafer is patterned using the deep reactive ion etching (DRIE) technique, and the seed layer is deposited using the physical vapor deposition (PVD) technique. Anode position optimization, a multi-step TSV filling process, additive concentration and plating current density optimization are conducted to enhance the filling efficiency while maintaining the void-free filling profile. The availability is verified by the wafer-segment plating of TSVs. The mechanism is investigated using linear sweep voltammetry (LSV), chronoamperometry, and a numerical simulation method.

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“…Through-Silicon-Vias (TSVs) provide a vertical electrical connection between multiple 3D die stacks. Recently, Samsung and IBM have demonstrated homogeneous stacked Dynamic Random Access Memory (DRAM) packages utilizing 3Di technology [3,4]. Additionally, several authors [5][6][7] have proposed heterogeneous chip stacking to integrate several chips of different functionality to form system in a package (SiP) technology.…”

Section: Introductionmentioning

confidence: 99%

High Frequency Electrical Characterization of 3d Signal/Ground Through Silicon Vias

Adamshick¹,

Carroll²,

Rao³

et al. 2014

PIER Letters

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Abstract-3D integration using through-silicon-vias (TSVs) is gaining considerable attention due to its superior packaging efficiency resulting in higher functionality, improved performance and a reduction in power consumption. In order to implement 3D chip designs with TSV technology, robust TSV electrical models are required. Specifically, due to the increase of signal speeds into the gigahertz (GHz) spectrum, a high frequency electrical characterization best describes TSV behavior. In this letter, 5 × 50 µm TSVs are manufactured using a via-mid integration scheme and characterized using S-parameters up to 65 GHz. At 50 GHz, the measured attenuation constant is 0.35 dB/via with a time delay of 0.7 ps/via.

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Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology

Cited by 17 publications

References 16 publications

Oxide-Oxide Thermocompression Direct Bonding Technologies with Capillary Self-Assembly for Multichip-to-Wafer Heterogeneous 3D System Integration

Oxide-Oxide Thermocompression Direct Bonding Technologies with Capillary Self-Assembly for Multichip-to-Wafer Heterogeneous 3D System Integration

Optimization of innovative approaches to the shortening of filling times in 3D integrated through-silicon vias (TSVs)

High Frequency Electrical Characterization of 3d Signal/Ground Through Silicon Vias

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