Novel quill-type cantilever-based surface patterning tools (SPTs) were designed and constructed for use in controlled placement of femtoliter volumes of biological molecules on surfaces for biological applications. These tools were fabricated from silicon dioxide using microelectromechanical systems (MEMS) techniques. They featured a 1 microm split gap, fluidic transport microchannels and self-replenishing reservoirs. Experimental trials were performed using these tools on NanoArrayer molecular deposition instrumentation. Cy3-streptavidin was loaded as a biological sample and patterned on an amine-reactive dithiobis-succinimidyl undecanoate (DSU) monolayer on gold. Results showed these tools were capable of generating high quality biological arrays with routine spot sizes of 2-3 microm. The spot size could potentially achieve sub-micron dimensions if these SPT designs are reduced in size by more precise microfabrication techniques. The geometric designs of these tools facilitated sample replenishment from the local reservoir on the cantilever which allowed printing of large numbers of spots without sample reloading.

The continuously decreasing size of integrated circuits is the driving force for the emergence of three-dimensional (3D) integration. The through-silicon via (TSV) is the heart of 3D IC/Si integrations, providing the shortest vertical interconnections, and it has a large number of significant advantages. In this paper, a new additive system specifically developed for high aspect ratio TSVs is introduced for TSV electroplating. A wafer is patterned using the deep reactive ion etching (DRIE) technique, and the seed layer is deposited using the physical vapor deposition (PVD) technique. Anode position optimization, a multi-step TSV filling process, additive concentration and plating current density optimization are conducted to enhance the filling efficiency while maintaining the void-free filling profile. The availability is verified by the wafer-segment plating of TSVs. The mechanism is investigated using linear sweep voltammetry (LSV), chronoamperometry, and a numerical simulation method.

Except for the internal factors such as properties of additives, adsorption or desorption mechanism, the external factors such as forced convection and environment temperature play an important role in achieving the void-free copper filling. In this paper, the effect of the external factors on the 3D integrated Cu-TSVs filling was investigated. For large dimension via (Ø 50 μm × 150 μm, AR∼3), forced convection factor decreases the via filling efficiency due to the convection-dependent adsorption (CDA) effect. While for the relatively small dimension via (Ø 20 μm × 120 μm, AR∼6), a modest forced convection is vitally necessary for the void-free filling. Too low or too high convection rate would cause voids during filling due to the lack of accelerator replenishment in the via bottom or the existence of the beak structure in the via opening, respectively. The inactive behavior of accelerator is the main reason for the filling model changes from V-shape model to the near-ideal bottom-up filling model. With an increase of the electrolyte temperature, elastic modulus of Cu-TSVs decreases sharply, while the hardness varies slightly. The hardness of the Cu-TSVs plated in a large range of electrolyte temperature (4-45 • C) is significantly higher than that of the bulk copper.For the integrated circuit, the rate of performance improvement slows down because industrial process integration has become increasingly difficult due to the factor that the size of CMOS scales down to its limit. 1 With an ever-increasing demand of small portable wireless electronic devices with a faster response, minimum package size and additional functionalities, a natural tendency to develop novel package and interconnection techniques appears. 2,3 A new concept of three-dimensional (3D) integration is proposed, which makes the interconnection of active devices in multilayer possible. 4 Through-silicon via (TSV) technology is the heart of 3D integration technology. 5 It provides the shortest vertical interconnections and has several significant advantages, such as high density, low energy consumption, high electrical performance, and low RC delay. Copper is used to replace aluminum and tungsten as the interconnect material due to its high reliability, low electrical resistance and good compatibility with integrated circuit modules. 6,7 However, as many other new technologies, Cu-TSV technology still face many critical issues. 5 Void-free filling is one of the toughest tasks in the TSV process flow. Super-filling model is an ideal model to achieve void-free or seamless Cu-TSV especially for high aspect ratio (AR) TSV. 8 For achieving super-filling model, several additives such as bis(3-sulfopropyl)disulfide (SPS), poly(ethylene glycol) (PEG), and Janus green B (JGB) are usually used in the plating bath. [8][9][10][11][12][13][14][15][16][17] The internal factors, such as the properties of additives, adsorption/desorption mechanism, direct current (DC) or periodic-pulsereverse (PPR) current, that affect void-free filling of TSVs are extensively i...

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