We have demonstrated fluidic chip self-assembly on Si wafers for fabricating three-dimensional integrated circuits. In this self-assembly technique, small droplets of hydrofluoric acid were employed to simultaneously align many millimeter-scale chips and directly bond them to the hydrophilic bonding areas formed on the host wafers by oxide–oxide bonding. The liquid surface tension enables many Si chips to be self-assembled with the highest alignment accuracy of 50 nm. In addition, many chips were tightly bonded to the hydrophilic bonding areas without applying a mechanical force after the liquid was evaporated at room temperature.

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We develop novel micro-bumping technology to realize small size, fine pitch and uniform height Cu/Sn bumps. Electroplated -evaporation bumping (EEB) technology, which is a combination of Cu electroplating and Sn evaporation, is developed to achieve uniform height of Cu/Sn bumps. We develop CMOS compatible dry etching processes for removing sputtered Cu/Ta layers to achieve small size and fine pitch Cu/Sn bump. 5 µm square and 10 µm pitch Cu/Sn micro-bumps are successfully fabricated for the first time. Bump height variation is 5 µm ±3 % (95%, 2σ), which is uniform compared to electroplated Cu/Sn bumps. We evaluate micro-joining characteristics of Cu/Sn micro-bumps. Good I-V characteristics are measured from the daisy chain consisting of 1500 bumps with 10 µm square and 20 µm pitch. Resistance of Cu/Sn bump is 35 mΩ/bump, which is very low value compared to electroplated Cu/Sn bumps.

In three-dimensional integration technology, through-silicon vias ͑TSVs͒ with a high aspect ratio in excess of 10 are required, due to a strong demand for a higher packing density. We achieved perfect conformal electroless plating of Cu by the addition of Cl − and bis͑3-sulfopropyl͒ disulfide to a standard plating bath. With this technology, the Cu thickness of the TSV sidewalls remained constant with depth, even for the TSV with an aspect ratio of 20. Perfect conformal plating is a promising technology that could lower the resistance of high aspect ratio TSVs.The formation of through-silicon vias ͑TSVs͒ to enable the stacking of multiple layers of thin Si substrates is a key technology for three-dimensional integration. It is expected that the minimum pitch of TSVs is smaller than 10 m, which will require the diameter of the TSVs to decrease below a few micrometers in the near future. 1,2 In such a structure, the TSV will take the place of a largescale integration circuit global interconnection. Cu filling of the TSV is an important technology because it enables a lower resistance TSV than chemical vapor deposition of tungsten ͑CVD-W͒ filling by an order of magnitude; however, there have been many technical problems in Cu filling of a high aspect ratio TSV. Cu electroplating technology has been studied extensively, 3 and a socalled superconformal deposition that enables a bottom-up fill of submicrometer vias has been proposed. [4][5][6][7][8][9][10][11][12][13] In Cu electroplating, the formation of a sputtered Cu seed layer is very difficult for a high aspect ratio via because the film thickness at the sidewall is much lower than on the flat surface. Therefore, conformal deposition using chemical vapor deposition of titanium nitride ͑CVD-TiN͒ or CVD-W was studied before Cu electroplating. 14-16 However, it is not easy to fill a high aspect ratio via by superconformal Cu electroplating.Cu electroless plating can result in good conformal deposition and is rather insensitive to the electrical conductivity of the seed layer. We found that a bottom-up fill was possible for a submicrometer ultra-large scale integration via using Cu electroless plating with the addition of a sulfuric organic compound with polyethylene glycol ͑PEG͒. We found that a sulfuric organic compound such as bis͑3-sulfopropyl͒ disulfide ͑SPS͒ acted as a strong inhibitor. 17,18 The diffusion of inhibitor molecules into the bottom of fine holes is limited, resulting in faster growth of Cu within the via. Furthermore, Cu can be deposited on TaN, WN, and W barrier layers without a Pd catalyst through displacement plating mechanisms. 19,20 In the preliminary stages of this study, we attempted to use an SPS-contained plating bath to fill TSVs. However, these additives were unable to achieve a bottom-up fill of high aspect ratio TSVs with diameters of a few micrometers. In this study, we investigated Cu-filling characteristics when adding Cl − as a third additive to a PEG and a sulfuric organic compound plating bath. ExperimentalWe prepared the TSV sam...

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