High Frequency Electrical Characterization of 3d Signal/Ground Through Silicon Vias

Abstract

Abstract-3D integration using through-silicon-vias (TSVs) is gaining considerable attention due to its superior packaging efficiency resulting in higher functionality, improved performance and a reduction in power consumption. In order to implement 3D chip designs with TSV technology, robust TSV electrical models are required. Specifically, due to the increase of signal speeds into the gigahertz (GHz) spectrum, a high frequency electrical characterization best describes TSV behavior. In this letter, 5 × 50 µm TSVs are manufactured using a via-mid integration scheme and characterized using S-parameters up to 65 GHz. At 50 GHz, the measured attenuation constant is 0.35 dB/via with a time delay of 0.7 ps/via.

A 60 GHz Millimeter-Wave Antenna Array for 3D Antenna-in-Package Applications

“…The patch elements with L patch =1.28 mm and W patch =2 mm are differentially fed from the Si interposer by using through-hole vias, a feed network, and BGAs. Further, no balun is required since the antenna elements are excited in the differential mode from the Si interposer [9,10]. Fig.…”

“…However, the SiP requires the usage of bond wires which are lossy and lead to path loss at such higher frequencies. Recently, a low loss 3D integrated method to interconnect heterogeneously stacked ICs within a SiP was presented in [9][10]. Instead of using lossy bond wires, Through Silicon Via (TSV) structures were employed to enable 3D vertically stacked ICs.…”