Three-Dimensional nand Flash for Vector–Matrix Multiplication

Wang, Panni; Xu, Feng; Wang, Bo; Gao, Bin; Wu, Huaqiang; He, Qian; Yu, Shimeng

doi:10.1109/tvlsi.2018.2882194

Cited by 85 publications

(43 citation statements)

References 12 publications

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“…Read disturb as well as program disturb can change the conductance of a synaptic device, reducing its accuracy. When implementing a synapse array with a NAND-type array, a pass voltage must be applied to de-selected cells of the same string during the inference operation, causing a read disturb ( Figure 10 a) [ 39 , 40 , 41 , 42 , 43 , 44 , 45 , 46 , 47 , 48 , 49 ]. However, in the proposed structure, there is little risk of a read disturb because there is no need to apply pass voltage to the word lines of de-selected cells ( Figure 10 b).…”

Section: Resultsmentioning

confidence: 99%

3D AND-Type Stacked Array for Neuromorphic Systems

et al. 2020

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NOR/AND flash memory was studied in neuromorphic systems to perform vector-by-matrix multiplication (VMM) by summing the current. Because the size of NOR/AND cells exceeds those of other memristor synaptic devices, we proposed a 3D AND-type stacked array to reduce the cell size. Through a tilted implantation method, the conformal sources and drains of each cell could be formed, with confirmation by a technology computer aided design (TCAD) simulation. In addition, the cell-to-cell variation due to the etch slope could be eliminated by controlling the deposition thickness of the cells. The suggested array can be beneficial in simple program/inhibit schemes given its use of Fowler–Nordheim (FN) tunneling because the drain lines and source lines are parallel. Therefore, the conductance of each synaptic device can be updated at low power level.

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Section: Resultsmentioning

confidence: 99%

3D AND-Type Stacked Array for Neuromorphic Systems

et al. 2020

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“…In the meantime, most of the works have been studied about synaptic devices using PCM, RRAM [6] and NOR flash memory [7], [8]. Another group used the measured characteristics of a single device to implement vector matrix multiplication in the NAND flash memory architecture [12]. However, all cells in NAND flash memory cannot be fully used as synaptic devices because the size of all synapse layers is determined by the number of word lines and the number of bit lines [12].…”

Section: Introductionmentioning

confidence: 99%

“…Another group used the measured characteristics of a single device to implement vector matrix multiplication in the NAND flash memory architecture [12]. However, all cells in NAND flash memory cannot be fully used as synaptic devices because the size of all synapse layers is determined by the number of word lines and the number of bit lines [12]. In addition, in the scheme of applying input voltages to word-lines [12], it is very difficult to allow analogue input values because of nonlinearity of I BL − V WL characteristics.…”

Section: Introductionmentioning

confidence: 99%

“…However, all cells in NAND flash memory cannot be fully used as synaptic devices because the size of all synapse layers is determined by the number of word lines and the number of bit lines [12]. In addition, in the scheme of applying input voltages to word-lines [12], it is very difficult to allow analogue input values because of nonlinearity of I BL − V WL characteristics. In this work, we propose a new operation scheme for implementing multi-layer neural networks using 2-D NAND flash memory cells as highdensity, reliable synaptic devices.…”

Section: Introductionmentioning

confidence: 99%

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Operation Scheme of Multi-Layer Neural Networks Using NAND Flash Memory as High-Density Synaptic Devices

Lee

Lim

Choi

et al. 2019

IEEE J. Electron Devices Soc.

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We propose a designing of multi-layer neural networks using 2D NAND flash memory cell as a high-density and reliable synaptic device. Our operation scheme eliminates the waste of NAND flash cells and allows analogue input values. A 3-layer perceptron network with 40,545 synapses is trained on a MNIST database set using an adaptive weight update method for hardware-based multi-layer neural networks. The conductance response of NAND flash cells is measured and it is shown that the unidirectional conductance response is suitable for implementing multi-layer neural networks using NAND flash memory cells as synaptic devices. Using an online-learning, we obtained higher learning accuracy with NAND synaptic devices compared to that with a memristor-based synapse regardless of weight update methods. Using an adaptive weight update method based on a unidirectional conductance response, we obtained a 94.19% learning accuracy with NAND synaptic devices. This accuracy is comparable to 94.69% obtained by synapses based on the ideal perfect linear device. Therefore, NAND flash memory which is mature technology and has great advantage in cell density can be a promising synaptic device for implementing high-density multi-layer neural networks. INDEX TERMS Neuromorphic, NAND flash memory, deep neural networks (DNNs), synaptic device, deep learning, multi-layer neural networks, hardware-based neural network.

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“…Among the possible candidates in the aforementioned computing architecture, in addition to the resistive random access memory (RRAM), phase‐change random access memory (PCRAM), and MRAM, the nanoscale flash memory has shown great prospects for the hardware implementation of deep learning due to its commercialized technology, ultrahigh integration density, and high‐speed transmission . Updated researches show that the nanoscale flash memory array could be used to improve the computing efficiency of vector‐by‐matrix multiplication and a fully connected neural network was demonstrated . Whereas, the hardware realization of fully connected layers is far from enough in multilayer neural network of deep learning due to the fact that over 90% of the computation is in the form of convolution .…”

Section: Introductionmentioning

confidence: 99%

Hardware Implementation of Energy Efficient Deep Learning Neural Network Based on Nanoscale Flash Computing Array

Xiang

Huang

Han

et al. 2019

Adv Materials Technologies

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memory [15][16][17] and spin-transfer torque (STT)-magnetic random access memory (MRAM), [18] to emulate the synapse and execute the vector-matrix multiplication efficiently.Among the possible candidates in the aforementioned computing architecture, in addition to the resistive random access memory (RRAM), phase-change random access memory (PCRAM), and MRAM, the nanoscale flash memory [19,20] has shown great prospects for the hardware implementation of deep learning due to its commercialized technology, ultrahigh integration density, and high-speed transmission. [21,22] Updated researches [23][24][25][26][27] show that the nanoscale flash memory array could be used to improve the computing efficiency of vector-by-matrix multiplication and a fully connected neural network was demonstrated. [25] Whereas, the hardware realization of fully connected layers is far from enough in multilayer neural network of deep learning due to the fact that over 90% of the computation is in the form of convolution. [28] In general, the overall technically demonstration of the nanoscale flash memory based hardware implementation of deep learning neural network that exploits the array configuration is still lacking.Here, we propose and demonstrate a new computing paradigm with hardware implementation of convolution, pooling, and fully connected layers of DNN based on the nanoscale flash computing array (NFCA), which is a universal and reconfigurable scheme. Multiple NFCAs combined with independent data processing blocks make it scalable to construct hardware DNN flexibly. We also show a low-cost, facile programming methodology to achieve precisely tuning of flash cells with small variability. The parallel computing of the preprogrammed NFCA leads to significant speed and energy efficiency increase. Furthermore, a five-layer DNN is simulated in simulation program with integrated circuit emphasis (SPICE) using the measured data from the fabricated 65 nm nor-type (NOR) flash memory to recognize Modified National Institute of Standards and Technology (MNIST) handwritten digit database and 97.8% recognition accuracy is achieved. Moreover, the optimized design of the DNN structure is proposed comprehensively to decrease the energy consumption and hardware cost. Deep learning neural network (DNN) can provide efficient approaches to process the increasing unstructured data, such as images, audio, and video. To improve the computing power and the energy efficiency of data processing in DNN, a universal and reconfigurable computing paradigm with the hardware implementation scheme including the convolution, pooling, and fully connected layers is developed based on nanoscale flash computing arrays, which can be massively fabricated. Via precisely tuning the threshold voltage, the fabricated 65 nm nanoscale flash cells can exhibit 16 levels (four bits) of storage states. To confirm the feasibility of the computing paradigm, an exemplary five-layer DNN is simulated based on the measured data from the nor-type (NOR) flash memory and exhibits 97.8% re...

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Three-Dimensional nand Flash for Vector–Matrix Multiplication

Cited by 85 publications

References 12 publications

3D AND-Type Stacked Array for Neuromorphic Systems

3D AND-Type Stacked Array for Neuromorphic Systems

Operation Scheme of Multi-Layer Neural Networks Using NAND Flash Memory as High-Density Synaptic Devices

Hardware Implementation of Energy Efficient Deep Learning Neural Network Based on Nanoscale Flash Computing Array

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