2017
DOI: 10.1088/1361-6668/aa6ef4
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Three-dimensional adiabatic quantum-flux-parametron fabricated using a double-active-layered niobium process

Abstract: Adiabatic quantum-flux-parametron (AQFP) is an ultra-low-power superconductor logic. In this study, we proposed and designed three-dimensional (3D) AQFP to achieve high circuit density and efficient interconnections. In 3D-AQFP, different AQFP logic circuits can be designed both over and under a ground plane (GP). The 3D-AQFP circuits are fabricated using the AIST 10 kA cm−2 Nb double gate process, in which two active layers are separated by a single GP. Followed by basic logic cell tests, we show an experimen… Show more

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Cited by 30 publications
(16 citation statements)
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“…The dimension of the RQFP cell is 180 μm × 145 μm, which is only 36% of that of the original design (270 μm × 270 μm) [10]. Further miniaturization might be possible by using a three-dimensional fabrication process [35]. I x1 and I x2 are the excitation currents, I ina through I inc are the input currents, which are applied to the RQFP cell through BUF chains, and V outx through V outz are the output voltages, which are generated by using the dc superconducting quantum interference devices (dc-SQUIDs) coupled to AQFPs.…”
Section: Methodsmentioning
confidence: 99%
“…The dimension of the RQFP cell is 180 μm × 145 μm, which is only 36% of that of the original design (270 μm × 270 μm) [10]. Further miniaturization might be possible by using a three-dimensional fabrication process [35]. I x1 and I x2 are the excitation currents, I ina through I inc are the input currents, which are applied to the RQFP cell through BUF chains, and V outx through V outz are the output voltages, which are generated by using the dc superconducting quantum interference devices (dc-SQUIDs) coupled to AQFPs.…”
Section: Methodsmentioning
confidence: 99%
“…All layers in our process are fully planarized. This allowed us successfully fabricate two fully independent layers of Josephson junctions, similar to the double-JJ-layer process demonstrated in [51]. Availability of multiple junction layers should enable increasing the integration scale of superconductor electronic circuits in a 3D manner.…”
Section: A Mo2n Kinetic Inductor Layer Placementmentioning
confidence: 96%
“…Considering the superconductor fabrication is still at an early development stage, the integration density is about 4× to 26× lower when comparing to the TSMC 40 nm CMOS technology. In the future, these numbers can be further reduced by introducing multi-layer techniques 29 and transformer-free AQFP technique 30 .…”
Section: Resultsmentioning
confidence: 99%