Superconductor Electronics Fabrication Process with MoNx Kinetic Inductors and Self-Shunted Josephson Junctions

Tolpygo, Sergey K.; Bolkhovsky, Vladimir; Oates, D.E.; Rastogi, Ravi; Zarr, Scott; Day, Alexandra; Weir, Terence J.; Wynn, Alex; Johnson, L. M.

doi:10.1109/tasc.2018.2809442

Cited by 49 publications

(33 citation statements)

References 42 publications

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“…Theoretical estimation [12] of the maximum density of SFQ-based circuits utilizing geometrical inductance of wires corresponds to already achieved ∼ 10 7 JJ/cm 2 . A further decrease of the line width and spacing is problematic because of nearly exponential growth in mutual inductance and cross talk between the inductors [13]. The main approach to shrink the inductor is related to the utilization of kinetic inductance.…”

Section: A Scaling Of Inductormentioning

confidence: 99%

Superconducting Circuits without Inductors Based on Bistable Josephson Junctions

et al. 2021

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Magnetic flux quantization in superconductors allows the implementation of fast and energy-efficient digital superconducting circuits. However, information representation in magnetic flux severely limits the functional density and is a long-standing problem. Here, we introduce the concept of superconducting digital circuits that do not utilize magnetic flux and have no inductors. We argue that neither the use of geometric nor kinetic inductance is promising for the scaling down of superconducting circuits. The key idea of our approach is the utilization of bistable Josephson junctions, allowing the representation of information through the Josephson energy. Since the proposed circuits are composed only of Josephson junctions, they can be called all-Josephson junction (all-JJ) circuits. We present a methodology for the design of circuits consisting of conventional and bistable junctions. We analyze the principles of the circuit's functioning, ranging from simple logic cells to an 8-bit parallel adder. The utilization of bistable junctions in the all-JJ circuits is promising for the simplification of schematics and a decrease of the JJ count, leading to space efficiency.

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Section: A Scaling Of Inductormentioning

confidence: 99%

Superconducting Circuits without Inductors Based on Bistable Josephson Junctions

et al. 2021

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“…The number of analog memory levels in the memory loop is determined by the inductance of the loop, which is easily set with the length of a wire. High-kinetic-inductance materials (Tolpygo et al, 2018 ) enable memory storage loops with over a thousand levels (10 bits) to be fabricated in an area of 5 μm × 5 μm.…”

Section: Synaptic Memorymentioning

confidence: 99%

Considerations for Neuromorphic Supercomputing in Semiconducting and Superconducting Optoelectronic Hardware

Primavera

Shainline

2021

Front. Neurosci.

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Any large-scale spiking neuromorphic system striving for complexity at the level of the human brain and beyond will need to be co-optimized for communication and computation. Such reasoning leads to the proposal for optoelectronic neuromorphic platforms that leverage the complementary properties of optics and electronics. Starting from the conjecture that future large-scale neuromorphic systems will utilize integrated photonics and fiber optics for communication in conjunction with analog electronics for computation, we consider two possible paths toward achieving this vision. The first is a semiconductor platform based on analog CMOS circuits and waveguide-integrated photodiodes. The second is a superconducting approach that utilizes Josephson junctions and waveguide-integrated superconducting single-photon detectors. We discuss available devices, assess scaling potential, and provide a list of key metrics and demonstrations for each platform. Both platforms hold potential, but their development will diverge in important respects. Semiconductor systems benefit from a robust fabrication ecosystem and can build on extensive progress made in purely electronic neuromorphic computing but will require III-V light source integration with electronics at an unprecedented scale, further advances in ultra-low capacitance photodiodes, and success from emerging memory technologies. Superconducting systems place near theoretically minimum burdens on light sources (a tremendous boon to one of the most speculative aspects of either platform) and provide new opportunities for integrated, high-endurance synaptic memory. However, superconducting optoelectronic systems will also contend with interfacing low-voltage electronic circuits to semiconductor light sources, the serial biasing of superconducting devices on an unprecedented scale, a less mature fabrication ecosystem, and cryogenic infrastructure.

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“…In some experiments we also implemented Nb/Ni/Mo2N/Nb junctions, making a SFS'S-type structure, where a 35-nm overlay of superconducting Mo2N [4] was deposited on the Ni surface prior to the Nb top electrode deposition. This amorphous overlay was used to decrease the Josephson critical current density of magnetic junctions by modifying the interface with the Nb top electrode.…”

Section: B Sis and Sfs Trilayers Fabricationmentioning

confidence: 99%

“…VER the past six years, our team has developed several nodes of the MIT Lincoln Laboratory (MIT LL) fabrication process for superconductor electronics (SCE), named SFQee, by progressively increasing the number of superconducting layers and decreasing the minimum linewidth [1]- [4]. This process development has been done within the framework of the IARPA C3 Program [5] for applications in energy efficient digital circuits based on different versions of pulsebased Single Flux Quantum (SFQ) logic.…”

Section: Introductionmentioning

confidence: 99%

“…Using this development approach, we have demonstrated circuits with close to one million JJs and circuit density over 1.3×10 6 JJ/cm 2 [7], [8]. To further increase the integration scale, we have recently introduced a fabrication process with self-shunted JJs and thin-film kinetic inductors [4], [9] in order to eliminate shunt resistors and reduce the area occupied by circuit inductors, the main impediments to increasing the integration scale of superconductor electronics [10]. The integration scale of SCE can be further increased by implementing multiple layers of active devices -Josephson junctions.…”

Section: Introductionmentioning

confidence: 99%

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Planarized Fabrication Process With Two Layers of SIS Josephson Junctions and Integration of SIS and SFS <italic>π</italic>-Junctions

Tolpygo

Bolkhovsky

Rastogi

et al. 2019

IEEE Trans. Appl. Supercond.

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We present our new fabrication Process for Superconductor Electronics (PSE2) that integrates two (2) layers of Josephson junctions (JJs) in a fully planarized multilayer process on 200-mm wafers. The two junction layers can be, e.g., conventional Superconductor-Insulator-Superconductor (SIS) Nb/Al/AlOx/Nb junctions with the same or different Josephson critical current densities, Jc. The process also allows integration of high-Jc Superconductor-Ferromagnet-Superconductor (SFS) or SFS'S JJs on the first junction layer with Nb/Al/AlOx/Nb trilayer junctions on the second JJ layer, or vice versa. In the present node, the SFS trilayer, Nb/Ni/Nb is placed below the standard SIS trilayer and separated by one niobium wiring layer. The main purpose of integrating the SFS and SIS junction layers is to provide compact π-phase shifters in logic cells of superconductor digital circuits and random access memories, and thereby increase the integration scale and functional density of superconductor electronics. The current node of the two-junction-layer process has six planarized niobium layers, two layers of resistors, and 350-nm minimum feature size. The target critical current densities for the SIS JJs are 100 μA/μm 2 and 200 μA/μm 2 . We present the salient features of the new process, fabrication details, and characterization results on two layers of JJs integrated into one process, both for the conventional and πjunctions.

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Superconductor Electronics Fabrication Process with MoNx Kinetic Inductors and Self-Shunted Josephson Junctions

Cited by 49 publications

References 42 publications

Superconducting Circuits without Inductors Based on Bistable Josephson Junctions

Superconducting Circuits without Inductors Based on Bistable Josephson Junctions

Considerations for Neuromorphic Supercomputing in Semiconducting and Superconducting Optoelectronic Hardware

Planarized Fabrication Process With Two Layers of SIS Josephson Junctions and Integration of SIS and SFS <italic>π</italic>-Junctions

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