Thin-film devices for low power applications

Monfray, S.; Fenouillet-Béranger, C.; Bidal, G.; Bœuf, F.; Denorme, S.; Huguenin, J.-L.; Samson, M.-P.; Loubet, N.; Hartmann, J.-M.; Campidelli, Y.; Destefanis, V.; Arvet, C.; Benotmane, K.; Clément, L.; Faynot, O.; Skotnicki, T.

doi:10.1016/j.sse.2009.12.013

Cited by 26 publications

(9 citation statements)

References 19 publications

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“…The drain-induced barrier lowering DIBL was also extracted through the V T variation in the linear (V T1 ) and saturation (V T2 ) region for the different devices under study and the results are shown in Table I for V DS =50 mV and V DS =1 V. The V T2 was extracted using the current level related with V T1 . The reduced DIBL values for a thinner silicon film are in agreement with the reduced output conductance, indicating that a smaller t Si is more effective for short channel effect reduction [11]. This behavior can be confirmed through Fig.…”

Section: Resultssupporting

confidence: 76%

Larger Intrinsic Voltage Gain Achieved with UTBOX SOI Devices and Thin Silicon Film

et al. 2012

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This work presents an analysis of the analog behavior of UTBOX SOI devices with different silicon film thickness. Thinner silicon films achieve a large intrinsic voltage gain due to the improved Early voltage, beyond the linearity improvement. This behavior is related with the increased gate coupling observed for thinner silicon films. An improved subthreshold slope and reduced DIBL values were also found. However, these devices show a degraded transconductance.

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Section: Resultssupporting

confidence: 76%

Larger Intrinsic Voltage Gain Achieved with UTBOX SOI Devices and Thin Silicon Film

et al. 2012

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“…Two etch processes are used: a) Electronic mail: romuald.blanc@st.com (1) The "high ion energy" process: CH 3 After both processes, a quasi in situ microwave plasma O 2 /N 2 post-treatment is performed using a remote microwave plasma reactor from Lam Research in order to remove carbon residues left on the silicon surface after the etching processes: O 2 4250 sccm/N 2 750 sccm/1000 mTorr/2500 W s . Two etch processes are used: a) Electronic mail: romuald.blanc@st.com (1) The "high ion energy" process: CH 3 After both processes, a quasi in situ microwave plasma O 2 /N 2 post-treatment is performed using a remote microwave plasma reactor from Lam Research in order to remove carbon residues left on the silicon surface after the etching processes: O 2 4250 sccm/N 2 750 sccm/1000 mTorr/2500 W s .…”

Section: A Spacer Etchingmentioning

confidence: 99%

“…2,3 To overcome these challenges, raised S/D regions have been introduced by an additional step of silicon epitaxy right after the formation of Si 3 N 4 gate spacers. After the multiple etch processes involved in the elaboration of the transistor's gate and spacers, the remaining silicon thickness can be as low as 3 nm.…”

Section: Introductionmentioning

confidence: 99%

Patterning of silicon nitride for CMOS gate spacer technology. II. Impact of subsilicon surface carbon implantation on epitaxial regrowth

Blanc

Jenny

Lagrasta

et al. 2014

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

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“…Additionally, the fully depleted intrinsic channel provides immunity to UTB devices from random dopant fluctuations [2]. Hence, these devices show excellent prospects for low power digital [3] as well as analog applications [4].…”

Section: Introductionmentioning

confidence: 99%

Reduced k-points based computationally efficient band structure approach for UTB device simulation

Solanki¹,

Mishra²,

Medury³

2021

Preprint

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The accurate calculation of channel electrostatics parameters, such as charge density and potential, in ultra-thin body (UTB) devices requires self-consistent solution of the Poisson’s equation and the full band structure, which is channel material and thickness dependent. For cubic crystals like silicon, the semi-empirical sp3d5s* tight-binding (TB) model is preferred in device simulations, over the density functional theory, to obtain the full band structure because of being computationally less intensive and equally accurate. However, the computational time of the TB model scales non-linearly with the channel thickness and becomes cumbersome for silicon, beyond 5 nm, primarily because of the increasing size of the TB hamiltonian that needs to be solved over the entire k-space, in the irreducible Brillouin zone. In this work, we precisely identify those k-points corresponding to the energies close to the band minima, where the Fermi-Dirac probability significantly affects electrostatics parameters. This enables us to demonstrate a computationally efficient approach based on solving the hamiltonian only on those reduced number of k-points. The rigorous benchmarking of the channel electrostatics parameters obtained from this approach is performed with results from accurate full band structure simulations showing excellent agreement over a wide range of channel thicknesses, oxide thicknesses, device temperatures and different channel orientations. By showing that the approach presented in this work is computationally efficient, besides being accurate, regardless of the number of atomic layers, we demonstrate its applicability for simulating UTB devices.

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Thin-film devices for low power applications

Cited by 26 publications

References 19 publications

Larger Intrinsic Voltage Gain Achieved with UTBOX SOI Devices and Thin Silicon Film

Larger Intrinsic Voltage Gain Achieved with UTBOX SOI Devices and Thin Silicon Film

Patterning of silicon nitride for CMOS gate spacer technology. II. Impact of subsilicon surface carbon implantation on epitaxial regrowth

Reduced k-points based computationally efficient band structure approach for UTB device simulation

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