1996
DOI: 10.1109/16.477592
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Thickness scaling limitation factors of ONO interpoly dielectric for nonvolatile memory devices

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Cited by 75 publications
(31 citation statements)
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“…5. Thanks to the silicon nitride interlayer, the minimum in the D it decreases from 10 12 for the SiO x / Si interface to 10 11 eV −1 cm −2 for both deposited SiN x and 30 s nitrided Si surface. The outcome of these measurements is that there is a significant improvement of the high-k / Si interface with nitride introduction.…”
Section: Resultsmentioning
confidence: 94%
See 1 more Smart Citation
“…5. Thanks to the silicon nitride interlayer, the minimum in the D it decreases from 10 12 for the SiO x / Si interface to 10 11 eV −1 cm −2 for both deposited SiN x and 30 s nitrided Si surface. The outcome of these measurements is that there is a significant improvement of the high-k / Si interface with nitride introduction.…”
Section: Resultsmentioning
confidence: 94%
“…7͒ and a k value ͑ϳ13͒, 8 suitable for these applications. 9 In flotox memories, the insulator is sandwiched between the poly-Si gates 10 and is called inter-poly-Si dielectric ͑IPD͒. In charge trap memories, the insulator or blocking oxide ͑BO͒ lies in contact with a silicon nitride trapping layer and a p-type metal.…”
Section: Introductionmentioning
confidence: 99%
“…Interpoly dielectric thickness heavily influences program/erase speed and the magnitude of read current for an industry-standard Flash cell [45]. Low defect density and long mean time to failure, together with charge retention capability, are important reliability issues.…”
Section: A Basic Operationsmentioning
confidence: 99%
“…A direct tunneling mechanism fixes the tunnel oxide limit to 6 nm, which needs to be increased more realistically up to 7-8 nm due to trap-assisted electron tunneling caused by oxide aging [69]. The scalability limit of the interpoly dielectric (ONO) has been reported to be around 12-13 nm [70]. These thicknesses can be combined to give an equivalent memory cell oxide (defined as tunnel oxide thickness divided by the coupling coefficient ), which sets the limit for the memory-cell poly length.…”
Section: Scaling Issuesmentioning
confidence: 99%
“…A conventional non-volatile flash device consists of a structure that can be summarized as Si/tunnel oxide/poly-Si floating gate/ interpoly dielectric/poly-Si control gate, where the tunnel and interpoly dielectrics (IPD) are typically a silicon oxide and oxide/nitride/oxide (O/N/O) stack, respectively. [1] Data are being stored in the floating gate as charge, which is transported through the tunnel dielectric by FowlerNordheim tunneling when a voltage is applied to the control gate.…”
Section: Introductionmentioning
confidence: 99%