Thermo-Mechanical Challenges in Stacked Packaging

Agonafer, Dereje; Kaisare, Abhijit; Hossain, M.M.; Lee, Yongje; Dewan-Sandur, Bhavani P.; Dishongh, Terry; Pekin, Senol

doi:10.1080/01457630701673170

Cited by 23 publications

(10 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…TSV (through Silicon Vias) may also help in reducing the package temperature by short circuiting the heat transfer path to the board. Previously it has been shown that TSVs aid in reducing the junction temperature for stacked packaging [2,12]. However, analysis still needs to be performed in order to determine the effect of advance cooling solutions on high power PoP.…”

Section: Power Casesmentioning

confidence: 99%

See 1 more Smart Citation

Thermal design optimization of a package on package

Menon

Karajgikar

Agonafer

2009

2009 25th Annual IEEE Semiconductor Thermal Measurement and Management Symposium

Self Cite

View full text Add to dashboard Cite

In the past decade, compact components such as Chip Scale Packages and flip chips were the work horses of miniaturization. However, emerging applications are now demanding even higher packaging density. In order to fulfill this requirement, three dimensional packaging was evolved. Advantages of three dimensional packaging structure include minimal conductor length and reduce speed limiting inter chip interconnects. In the past, this packaging approach was relegated to memory devices with relatively low power (flash). Recent focus, however, has been to extend the applications of stacked packages to include high performance memory, DRAM, logic-memory stack, system in a package etc. Stacked packages can be package-on-package or die stacked (with several dice inside the same casing) or both. It is common in a mobile phone that the stacked CSP is mounted on a circuit board and there is no space for air circulation. Depending on the power, due to the torturous heat flow path, it can result in high temperatures of the packaged die and the thermal specifications of the package can be easily exceeded. Hence there is a need for thermal simulation of a variety of packaging architecture for applications of interest. The objective of this paper was to perform thermal characterization of a commercially viable PoP. In order to model this PoP, flip chip logic die package was considered as the bottom package and two memory dice stacked package was considered as the top package. Eleven different scenarios were taken into consideration for the numerical analysis. Permutations of 0.1, 0.2, 0.3 and 1, 2 and 3 W memory die and logic die was considered respectively Additional two cases are also described. Steady state analysis was performed based on which guidelines were provided. For the analysis commercially available FEA tool was considered.

show abstract

Section: Power Casesmentioning

confidence: 99%

“…Different die arrangements such as rotated, staggered, pyramid etc. are commonly adopted [2,3]. In PoP, two entirely different packages are mounted on each other with electrical and possible thermal interconnects.…”

Section: Introductionmentioning

confidence: 99%

Thermal design optimization of a package on package

Menon

Karajgikar

Agonafer

2009

2009 25th Annual IEEE Semiconductor Thermal Measurement and Management Symposium

Self Cite

View full text Add to dashboard Cite

show abstract

“…Thermal management issues in the 3D stacks are considered as one of the main challenges for 3D integrations [3,4,5]. These issues are caused by the use of bonding adhesives with poor thermal conductivity, by the vertical stacking of the chips and by the reduced thermal spreading due the aggressively thinned dies (down to 25 µm).…”

Section: Introductionmentioning

confidence: 99%

Characterization of the thermal impact of Cu-Cu bonds achieved using TSVs on hot spot dissipation in 3D stacked ICs

Oprins

Cherman

Vandevelde

et al. 2011

2011 IEEE 61st Electronic Components and Technology Conference (ECTC)

View full text Add to dashboard Cite

3D-IC stacking is a promising technique for miniaturization and performance enhancement of electronic systems. The complexity of the interconnect structures, combined with the reduced thermal spreading in the thinned dies used for the stacking and the poorly thermally conductive adhesives adopted for bonding the dies in the stack complicate the modeling of the thermal behavior of 3D ICs. The same amount of energy dissipation will lead to higher temperatures and a more pronounced temperature peak in a stacked die with respect to a single die. Therefore, the thermal behavior in a 3D-IC needs to be studied thoroughly. In this paper, the impact of TSVs and the Cu-Cu bonding on the temperature profile of the top and bottom die of a 3D stack is characterized by using dedicated test chips with integrated thermal heaters and temperature sensors. A specific experimental set-up is conceived and used to evaluate and improve the thermal models for the 3D stacks.

show abstract

“…Thermal management issues are considered one of the major challenges for 3D-integration [2,3,4]. These issues are caused by the use of bonding adhesives with poor thermal conductivity, by the vertical stacking of the chips and by the reduced thermal spreading due the aggressively thinned dies (down to 25 µm).…”

Section: Introductionmentioning

confidence: 99%

Transient analysis based thermal characterization of die-die interfaces in 3D-ICs

Oprins

Cherman

Rebibis

et al. 2012

13th InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems

View full text Add to dashboard Cite

In this paper, we present a novel methodology using a thermal test chip to characterize the bulk thermal conductivity and the thermal contact resistance of underfill materials in diedie interfaces of 3D stacks for application-realistic test conditions. Since a silicon chip is used, the thermal properties can be extracted for the same material interfaces (finishing of the Si surface) and the same processing conditions (bonding and temperature profile during curing of the underfill material) as in the intended application. In the proposed methodology, transient thermal measurements obtained using a test chip with integrated heaters and sensors, are combined with thermal finite element simulations to extract the thermal properties.The proposed method is applied to extract the thermal properties and compare the thermal performance of 8 underfill materials. The materials are thermally characterized before and after curing. It is shown that the comparison of the temperature profiles before and after curing can indicate void for matio n or delamination dur ing the curing stage.

show abstract

Thermo-Mechanical Challenges in Stacked Packaging

Cited by 23 publications

References 3 publications

Thermal design optimization of a package on package

Thermal design optimization of a package on package

Characterization of the thermal impact of Cu-Cu bonds achieved using TSVs on hot spot dissipation in 3D stacked ICs

Transient analysis based thermal characterization of die-die interfaces in 3D-ICs

Contact Info

Product

Resources

About