Characterization of the thermal impact of Cu-Cu bonds achieved using TSVs on hot spot dissipation in 3D stacked ICs

Oprins, Herman; Cherman, Vladimir; Vandevelde, Bart; Torregiani, C.; Stucchi, M.; Plas, G. Van der; Marchal, Pierre; Beyne, Eric

doi:10.1109/ectc.2011.5898612

Cited by 16 publications

(6 citation statements)

References 20 publications

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“…It is important to recall that due to aspect ratio limitations, high-density TSVs interconnections require aggressively thinned silicon wafers. Simulation and experimental results in [7] indicate that the hotspot temperature on a 25µm thick die in the 3D stack is approximately 2x higher compared to a 2D reference case. Fig.…”

Section: B Die Thicknessmentioning

confidence: 93%

Thermal performance of 3D ICs: Analysis and alternatives

Santos

Vivet

Colonna

et al. 2014

2014 International 3D Systems Integration Conference (3DIC)

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3D ICs are assumed to suffer from stronger thermal issues when compared to equivalent implementations in traditional single-die integration technologies. Based on this assumption, heat dissipation is frequently pointed as one of the remaining challenges in the promising 3D integration technology. This work brings an overview of the thermal impact of the 3D integration technology, providing means to investigate causes and alternative solution for the existing thermal issues in 3D ICs. A complete chip-package-board system is used to evaluate the thermal performance of a memory-on-logic 3D circuit. Thermal simulations and silicon measurements from two fabricated versions of a SoC instrumented with integrated heaters and thermal sensors are compared to reveal the temperature profile changes resulting from 3D integration. This work also provides a comprehensive discussion of the four main aspects differentiating heat dissipation in 3D ICs: chip footprint, die thickness, inter-die interface and TSVs. This study demonstrates, for instance, that non-thinned stacked dies may act as heat spreaders and help to alleviate hotspot issues while TSVs are in fact not effective for thermal mitigation. Lastly, this work proposes the use of graphitebased heat spreaders as an alternative to compensate the poor heat dissipation properties exhibited in 3D ICs. Simulation results show a temperature reduction of up to 45ºC and suggest this is a potential cost-effective method for thermal management. The discussion presented in this work aims to understand the thermal impact of technology parameters inherent in 3D integration and supports system architects and designers to take early design decisions and prevent thermal issues.I.

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Section: B Die Thicknessmentioning

confidence: 93%

Thermal performance of 3D ICs: Analysis and alternatives

Santos

Vivet

Colonna

et al. 2014

2014 International 3D Systems Integration Conference (3DIC)

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“…Fig.2. Cross-section of direct Cu-Cu bonding [10] (left) and microbump [7] (right) die-die interface.…”

Section: Introductionmentioning

confidence: 99%

“…This paper focuses on the thermal characterization of the underfill materials used in combination with microbumps. In [10] the thermal impact of a die -die interface with Cu-Cu bonds is studied. In that case the thickness of the die -die interface is typically in the order of several hundreds of nm to 1µm.…”

Section: Introductionmentioning

confidence: 99%

Transient analysis based thermal characterization of die-die interfaces in 3D-ICs

Oprins

Cherman

Rebibis

et al. 2012

13th InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems

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In this paper, we present a novel methodology using a thermal test chip to characterize the bulk thermal conductivity and the thermal contact resistance of underfill materials in diedie interfaces of 3D stacks for application-realistic test conditions. Since a silicon chip is used, the thermal properties can be extracted for the same material interfaces (finishing of the Si surface) and the same processing conditions (bonding and temperature profile during curing of the underfill material) as in the intended application. In the proposed methodology, transient thermal measurements obtained using a test chip with integrated heaters and sensors, are combined with thermal finite element simulations to extract the thermal properties.The proposed method is applied to extract the thermal properties and compare the thermal performance of 8 underfill materials. The materials are thermally characterized before and after curing. It is shown that the comparison of the temperature profiles before and after curing can indicate void for matio n or delamination dur ing the curing stage.

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“…To enhance the integrated circuit performance besides of 2 dimensional scaling 3D chip and wafer stacking technology with through silicon via (TSV) is intensely developed around the world, which will enable the large transferring signal bandwidth, the low power consumption, the small form factor and so on [1][2]. Low resistant electrical interconnection between the chips is very important, which mainly depends on the conductivity of interconnecting material and dimensions.…”

Section: Introductionmentioning

confidence: 99%

Low temperature touch down and suppressing filler trapping bonding process with a wafer level pre-applied underfilling film adhesive

Nonaka

Niizeki

Asahi

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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Flip chip bonding process of the chip touch down at 40 o C and suppressing the material trapping at the joint area with the wafer level NCF (Non conductive film), which is pre applied underfilling film adhesive, has been investigated. The test vehicle wafer has 25 μm diameter and 50 μm height bumps which are 10 μm height Cu pillar and 40 μm height Sn-Ag solder cap. The bump pitch was 200 μm. The 55 μm thickness 50 wt% filler loaded NCF was laminated on the wafer and then the surface was planarized with the bump solder layer exposing by the bit cutting technique. Such prepared chip was bonded as the top chip to the bottom chip which has the 25 μm diameter pad of 3 μm Cu bottom, 2 μm Ni middle and 0.1 μm Au top. To insert the sticking step in the bonding process, which melts and flows down the NCF underneath the top chip to the bottom chip partially, the chips were held well the aligned position during the successive processes. The gang bonding possibility was also proved with the four chips together bonding. PCT (pressure cooker test, 121 o C and 100%Rh for 168 hours) was performed to the gang bonded samples. By shortening the joint formation step time form 25 to 5 seconds Cu diffusion into the solder bulk area was suppressed and the durable joint to the PCT was formed. It was confirmed by the cross sectional observations.

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Characterization of the thermal impact of Cu-Cu bonds achieved using TSVs on hot spot dissipation in 3D stacked ICs

Cited by 16 publications

References 20 publications

Thermal performance of 3D ICs: Analysis and alternatives

Thermal performance of 3D ICs: Analysis and alternatives

Transient analysis based thermal characterization of die-die interfaces in 3D-ICs

Low temperature touch down and suppressing filler trapping bonding process with a wafer level pre-applied underfilling film adhesive

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