Thermally Stable N-Metal Gate MOSFETs Using La-Incorporated HfSiO Dielectric

Alshareef, Husam N.; Harris, H. R.; Wen, Huang-Chun; Park, C.; Huffman, C.; Choi, Kwang-Il; Luan, H.F.; Majhi, P.; Lee, B.; Jammy, R.; Lichtenwalner, Daniel J.; Kingon, Angus I.

doi:10.1109/vlsit.2006.1705190

Cited by 60 publications

(46 citation statements)

References 4 publications

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“…Xu [37] reported the fabrication of HfLaON gate dielectrics with an EOT of 0.62 nm to suppress tunneling leakage. La doping was demonstrated to enhance the k value of the dielectrics and Alshareef et al [23] observed that the addition of Al into Hf-based high-k materials could passivate the oxygen vacancy 0 V  which induced midgap states but there was with little influence by other aspects of the defects . Aluminum has also been observed to enhance the crystallization temperature of Hf-based high-k dielectrics [38].…”

Section: Dual-dipole Formation In Mos Stackmentioning

confidence: 99%

Interface dipole engineering in metal gate/high-k stacks

et al. 2012

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Although metal gate/high-k stacks are commonly used in metal-oxide-semiconductor field-effect-transistors (MOSFETs) in the 45 nm technology node and beyond, there are still many challenges to be solved. Among the various technologies to tackle these problems, interface dipole engineering (IDE) is an effective method to improve the performance, particularly, modulating the effective work function (EWF) of metal gates. Because of the different electronegativity of the various atoms in the interfacial layer, a dipole layer with an electric filed can be formed altering the band alignment in the MOS stack. This paper reviews the interface dipole formation induced by different elements, recent progresses in metal gate/high-k MOS stacks with IDE on EWF modulation, and mechanism of IDE. high-k dielectrics, metal gate, interface dipole, MOS stack, effective work function Citation:Huang A P, Zheng X H, Xiao Z S, et al. Interface dipole engineering in metal gate/high-k stacks. Chin Sci Bull, 2012, 57: 28722878, doi: 10.1007/s11434-012-5289-6As poly-Si/SiO 2 is replaced by metal gate/high-k stacks in the 45 nm MOS technological node and beyond, the interface becomes more complicated and there are still many challenges to be solved [1,2], such as the flatband voltage shift (V fb shift) [3]. Hence, the properties of the high-k layer must be reconsidered carefully. It has recently been reported that the interface dipole can induce potential difference across the interface and change the band alignment of the MOS stack, and this phenomenon can be exploited to modulate the V fb shift [4][5][6]. Elemental doping can also improve the performance of the high-k layer. Interface dipole engineering (IDE) by varying the dopants or inserting capping layers has attracted much attention in MOS technology. Not only can this technique control the V fb shift, but also the properties of the high-k dielectrics can be improved [7]. This paper reviews the formation of interface dipole, recent research progresses on IDE and effective work function (EWF) modulation, as well as mechanism of IDE in metal gate/high-k MOS stacks. Interface dipole formation in MOS stackTo control the threshold voltage (V th ), work function of a metal gate should be near the conduction band of Si (~4.3 eV) for nMOS and valence band (~5.2 eV) for pMOS. However, only very few metals can satisfy these requirements and furthermore, when a metal is in contact with the high-k layer, its Fermi-level will tend to be at the neutral level of the high-k layer. This phenomenon is called Fermi-level pinning (FLP) which causes EWF of the nMOS (pMOS) to be much greater (smaller) than the corresponding work function in vacuum [8]. The electron density in the metal gate can also influence the EWF [9]. Stacked metal layers used in the gate structure have been investigated. Misra et al. [10] reported that a metal gate stack using Ru-Ta alloys could yield a work function compatible with nMOS. Lin et al. [11] implanted N into a Mo gate that was

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Section: Dual-dipole Formation In Mos Stackmentioning

confidence: 99%

Interface dipole engineering in metal gate/high-k stacks

et al. 2012

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“…3(a) and (b), respectively. A slight peak mobility degradation of ∼12% is observed by using La 2 O 3 /SiO x IL, as compared to the reference sample, which is likely due to the high La concentration that is close to the Si channel [4]. PBTI measurements were done at 110 • C by using sense-and-measure technique and monitoring I D with a 0.1-s measuring step [11], and the result is shown in Fig.…”

Section: Resultsmentioning

confidence: 99%

Electrical Properties of Low-$V_{T}$ Metal-Gated n-MOSFETs Using $\hbox{La}_{2}\hbox{O}_{3}/\hbox{SiO}_{x}$ as Interfacial Layer Between HfLaO High-$\kappa$ Dielectrics and Si Channel

Chang

Hónɡ

Adelmann

et al. 2008

IEEE Electron Device Lett.

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In this letter, we report that by employing the La 2 O 3 /SiO x interfacial layer between HfLaO (La = 10%) high-κ and Si channel, the Ta 2 C metal-gated n-MOSFETs V T can be significantly reduced by ∼350 mV to 0.2 V, satisfying the low-V T device requirement. The resultant n-MOSFETs also exhibit an ultrathin equivalent oxide thickness (∼1.18 nm) with a low gate leakage (J G = 10 mA/cm 2 at 1.1 V), good drive performance (I on = 900 µA/µm at I soff = 70 nA/µm), and acceptable positive-bias-temperature-instability reliability.Index Terms-HfLaO, La 2 O 3 /SiO x interfacial layer (IL), low-V T n-MOSFETs, Ta 2 C.

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“…A smooth interface between the NiSi and the dielectrics is revealed for both devices. From the dielectrics thickness comparison on both devices, it clearly suggests that a uniform DySiON dielectric layer is formed due to the intermixing between Dy 2 O 3 and SiON dielectrics after the thermal treatment [8].…”

Section: Device Fabrication Setupmentioning

confidence: 98%

Demonstration of Low $V_{t}$ Ni-FUSI N-MOSFETs With SiON Dielectrics by Using a $\hbox{Dy}_{2}\hbox{O}_{3}$ Cap Layer

Hónɡ

Chang

Veloso

et al. 2007

IEEE Electron Device Lett.

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This letter reports a novel approach to achieve low threshold voltage (V t ) Ni-FUlly-SIlicide (FUSI) nMOSFETs with SiON dielectrics. By using a Dysprosium-oxide (Dy 2 O 3 ) cap layer with a thickness of 5 Å on top of the SiON host dielectrics, V t,lin of 0.18 V for long-channel devices (L g = 1 µm) using NiSi-FUSI electrode is obtained, satisfying the high-performance device requirements. The V t modulation due to the Dy 2 O 3 cap layer is also maintained in the short-channel devices (with an L g,min of 90 nm as demonstrated in this letter). In particular, approximately 150× reduction in gate leakage current is seen while preserving the dielectric capacitance equivalent thickness after adding the Dy 2 O 3 cap layer on SiON dielectrics, likely due to a high-κ layer (DySiON) formation during device source/drain activation process. We also report that the Dy 2 O 3 layer does not vitally degrade the device reliability, such as positive-bias temperature instability and time-dependant dielectrics breakdown.Index Terms-Dysprosium-oxide (Dy 2 O 3 ) cap layer, low V t nMOSFETs, Ni-FUlly-SIlicide (FUSI), SiON.

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Thermally Stable N-Metal Gate MOSFETs Using La-Incorporated HfSiO Dielectric

Cited by 60 publications

References 4 publications

Interface dipole engineering in metal gate/high-k stacks

Interface dipole engineering in metal gate/high-k stacks

Electrical Properties of Low-$V_{T}$ Metal-Gated n-MOSFETs Using $\hbox{La}_{2}\hbox{O}_{3}/\hbox{SiO}_{x}$ as Interfacial Layer Between HfLaO High-$\kappa$ Dielectrics and Si Channel

Demonstration of Low $V_{t}$ Ni-FUSI N-MOSFETs With SiON Dielectrics by Using a $\hbox{Dy}_{2}\hbox{O}_{3}$ Cap Layer

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