Thermal implications of mobile 3D-ICs

Abstract

In this paper, we introduce a fast and accurate 3D thermal analysis methodology for sequential face-to-back (F2B) and parallel face-to-face (F2F) 3D integration technologies. Our proposed models take design floorplan and the corresponding power map with temperature-dependent leakage power component and accurately estimate the temperature of any given location in the design. We show that our models are within less than 1% of commercial-grade finite-volume models while they are 100X faster. In addition, we demonstrate the minimum power reduction required in mobile 3D-ICs to achieve similar thermal behaviour of that of the corresponding 2D-ICs. Subsequently, we provide guidelines on 3D partitioning / floorplanning to further improve thermal profile of 3D-ICs.

3d Vlsi

“…In addition to improve area and wirelegnth metrics, 3D floorplanner should also avoid placement of high-power consuming blocks on top of each other. Recently, [7] shows that appropriate 3D floorplanning can improve thermal profile of 3D designs beyond the counterpart 2D designs.…”

“…An example of (a) 2D block partitioning and floorplanning (b) 2D block partitioning with 3D floorplanning (c) 3D block partitioning with 2D floorplanning and (d) combination of 2D and 3D block partitioning with 3D floorplanning[7].…”