Thermal and plasma treatments for improved (sub-)1 nm equivalent oxide thickness planar and FinFET-based replacement metal gate high-k last devices and enabling a simplified scalable CMOS integration scheme

Abstract

We report on aggressively scaled replacement metal gate, high-k last (RMG-HKL) planar and multi-gate fin field-effect transistor (FinFET) devices, systematically investigating the impact of post high-k deposition thermal (PDA) and plasma (SF6) treatments on device characteristics, and providing a deeper insight into underlying degradation mechanisms. We demonstrate that: 1) substantially reduced gate leakage (J G) and noise can be obtained for both type of devices with PDA and F incorporation in the gate stack by SF6, without equivalent oxide thickness (EOT) penalty; 2) SF6 enables improved mobility and reduced interface trapped charge density (N it) down to narrower fin devices [fin width (W Fin) ≥ 5 nm], mitigating the impact of fin patterning and fin sidewall crystal orientations, while allowing a simplified dual-effective work function (EWF) CMOS scheme suitable for both device architectures; 3) PDA yields smaller, in absolute values, PMOS threshold voltage |V T|, and substantially improved reliability behavior due to reduction of bulk defects.

Importance of Si surface flatness to realize high-performance Si devices utilizing ultrathin films with new material system

“…With the device scaling, for example, thinner gate insulator will be required such as less than 0.5 nm of equivalent oxide thickness (EOT) or below [1]. In order to realize the adequate scaled device, various new materials have been introduced in the scaled MOSFETs [2,3]. Fig.…”

“…HfO 2 , La 2 O 3 , Al 2 O 3 etc.) to make the EOT smaller with increase of physical thickness compared that of SiO 2 to decrease the gate leakage current [3,4,5,6]. Metal gate electrodes (e.g.…”

“…TiN, TaN, W, Pt, Ir etc.) will be introduced instead of heavily doped poly-Si gate electrode to suppress the depletion which leads to the increase of EOT [3,7]. Various metal gate/high-k gate stack structures have been reported so far, and ultrathin EOT of 0.2 nm has been achieved [4].…”

Novel Band-Edge Work Function Performance Modulation via NPT with PMOS1st/NMOS1st Laminated Stack for PMOS Low Power Target

“…10 The general strategy to realize multi-V T is focusing on gate laminated stacks, which is generally utilized as dual-work function metal stacks. [11][12][13][14][15] Therefore, according to the sequence of deposition p-and n-type work function metal in the RMG-HKMG process flow, the current integration strategy to achieve specific V T target can be divided into PMOS first (PMOS 1st ), and NMOS first (NMOS 1st ) integration schemes. In the PMOS 1st integration, 16,17 the PMOS gate trench is first filled with p-type work function metal layer, and additionally with n-type work function metal layer under NMOS gate trench filling, while NMOS only possesses n-type work function layer.…”

Comparative Investigation of Flat-Band Voltage Modulation by Nitrogen Plasma Treatment for Advanced HKMG Technology

“…As the physical gate length of RMG scaling down to below 14nm for sub-7nm technology node, the gap filling volume becomes rigorous and the V T tuning capability by this method turns inadequate for CMOS IC applications. 8 To realize a large V T adjustment range with a more simplified stack structure and film thickness control process as well as no degradation in mobility and reliability of devices, a series of novel methods have been proposed, including decoupled plasma nitridation, 9,10 impurity doped high-k dielectric, 11,12 SiH 4 -soak of barrier layer, 13 ion implantation in work function metal, 14,15 and high-k capping layer with dipole. 16 Among these new technologies, the approach of nitrogen plasma treatment on the multi-layer high-k/metal-gate (HKMG) stack demonstrates a simplified process cost and a strong modulation ability; several initial experimental results and hypothetical predictions are published.…”