Importance of Si surface flatness to realize high-performance Si devices utilizing ultrathin films with new material system

Abstract

The importance of Si surface flatness on metal-oxide-semiconductor field-effect transistor (MOSFET) characteristics with ultrathin hafnium oxynitride (HfON) high-k gate insulator formed by electron cyclotron resonance (ECR) plasma sputtering was described. The surface roughness of Si substrate was reduced by Ar/4.9%H 2 annealing utilizing conventional rapid thermal annealing (RTA) system. Si surface root-mean-square (RMS) roughness was well controlled by changing the annealing temperature from 700 to 1000°C. Si surface RMS roughness after 1000°C/1 hr annealing was 0.078 nm for Si(100) and 0.082 nm for Si(110), respectively. Clear dependence of electrical characteristics of MOS diodes such as equivalent oxide thickness (EOT) and leakage current on the surface RMS roughness of Si(100) and Si(110) was observed, and the electrical characteristics were remarkably improved by decreasing of surface RMS roughness. The MOSFET characteristics with HfON gate insulator fabricated on Si(100) substrates after flattening process were also improved.

Variability Improvement by Si Surface Flattening of Electrical Characteristics in MOSFETs With High-k HfON Gate Insulator

“…The nitrogen concentration in HfON layer was approximately 10%. The EOTs of HfON layer were 0.98 nm for the sample without (w/o) annealed, and 0.78 nm for the sample with Ar/4.9%H2 annealed, respectively [24,26]. Finally, the contact hole was patterned and Al electrodes were formed for gate (G) and S/D by thermal evaporation.…”

“…We have reported that the Si(100) and Si(110) surfaces were able to be flattened by Ar/4.9%H2 annealing utilizing conventional rapid thermal annealing (RTA) system [24]. The annealing was carried out at 700-1000 o C for 60 min, and minimum surface roughness was obtained when the annealing temperature was 1000 o C [24].…”

“…The annealing was carried out at 700-1000 o C for 60 min, and minimum surface roughness was obtained when the annealing temperature was 1000 o C [24]. Furthermore, it was found that the device characteristics of MOSFETs with high-k HfON gate insulator formed by electron cyclotron resonance (ECR) plasma sputtering were significantly improved with decreasing the surface roughness [24][25][26][27]. In this paper, we have investigated the variability improvement of MOSFET characteristics with high-k HfON gate insulator by Si surface flattening utilizing Ar/4.9% ambient annealing at 1000 o C for 60 min.…”

“…Fig. 1 shows the typical gate-last n-channel MOSFET fabrication process used in this research [24,25]. After the active region isolation by local oxidation of Si (LOCOS), channel stop ion implantation was carried out at 100 keV with dose of 1x10 14 cm -2 for BF3 to form the heavily doped p + region underneath the field oxide.…”

In-situ formation of Hf-based MONOS structures for non-volatile memory applications

“…We have reported various Hf-based high-k gate insulators and also in-situ formation of HfN x (x < 1:0) gate electrode on the Hf-based high-k gate insulator [10,11,12,13,14]. It was found that the in-situ formation of HfN x (x < 1:0) gate electrode improved the electrical characteristics of Hf-based high-k gate insulator [13].…”