The Separation Measurement of $P$ -Hit and $N$ -Hit Charge Sharing With an “S-Like” Inverter Chains Test Structure

Huang, Pengcheng; Chen, Shuming; Chen, Jianjun; Liang, Bin; Song, Ruiqiang

doi:10.1109/tns.2017.2677904

Cited by 10 publications

(7 citation statements)

References 20 publications

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“…We simulated an ion strike at the center of the drain of the struck transistor normally. Similar to our previous works [20][21][22][23][24][25], the included physical models are: (a) Fermi-Dirac statistics, (b) the doping-dependent carrier mobility model with high electric field saturation, carrier-carrier scattering as well as interface scattering; (c) carrier recombination model: doping-dependent SRH and Auger recombination; (d) the effect of bandgap narrowing; (e) hydrodynamic carrier transport model; (f) and other models are configured with default models and parameters.…”

Section: Simulation Detailssupporting

confidence: 78%

Bulk Bias as an Analog Single-Event Transient Mitigation Technique with Negligible Penalty

et al. 2019

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In analog circuit design, the bulks of MOSFETs can be tied to their respective sources to remove body effect. This paper models and analyzes the sensitivity of single-event transients (SETs) in common source (CS) amplifier with bulk tied to source (BTS) in 40 nm twin-well bulk CMOS technology. The simulation results present that the proposed BTS radiation-hardened-by-design (RHBD) technique can reduce charge collection and suppress the SET induced perturbation effectively in various input conditions of the circuit. The detailed analysis shows that the mitigation of SET is primarily due to the forward-bias of bulk potential. This technique is universally applicable in radiation-hardening design for analog circuits with negligible penalty.

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Section: Simulation Detailssupporting

confidence: 78%

Bulk Bias as an Analog Single-Event Transient Mitigation Technique with Negligible Penalty

et al. 2019

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“…Three-dimensional mixed-mode TCAD simulation has been proven to be a useful means of investigating single-event effects (SEEs) in ICs [4,9,12,13,14,15,16,17,18,19]. In this work, we have adopted a Sentaurus TCAD from Synopsys, using 65 nm CMOS technology.…”

Section: Simulation Setupmentioning

confidence: 99%

A dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination

Liu

Peng

Lin

et al. 2018

IEICE Electron. Express

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A dual-output design of inverter chain that is hardened against P-hit single-event transient (SET) is proposed in this paper. The output nodes of the proposed inverter chain are hardened by dual-output topological structure design and stacked PMOSs with isolation. The simulation results based on a 65 nm CMOS technology suggest that the proposed design can eliminate SET pulse significantly. In comparison with the conventional inverter chain and inverter chain using the source-isolation technique, the proposed design is capable of maintain the output steadily irrespective of whether an ion hits "0" or hits "1", i.e., the struck node is at logic "0" or logic "1". Besides, the SET pulse occurring at any stage of inverter chains with the proposed methodology will not disturb the final output, as long as it does not occur at the final stage.

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“…However, due to the lack of heavy ion-induced sensitive area data, it is difficult for circuit designers to determine the required increased distance. Some previous works have reported standard cell-based test circuits to indirectly investigate the heavy ion-induced sensitive area [13,14]. However, it is hard to accurately obtain the sensitive area data due to the large layout area of standard cells.…”

Section: Introductionmentioning

confidence: 99%

TAISAM: A Transistor Array-Based Test Method for Characterizing Heavy Ion-Induced Sensitive Areas in Semiconductor Materials

et al. 2022

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The heavy ion-induced sensitive area is an essential parameter for space application integrated circuits. Circuit Designers need it to evaluate and mitigate heavy ion-induced soft errors. However, it is hard to measure this parameter due to the lack of test structures and methods. In this paper, a test method called TAISAM was proposed to measure the heavy ion-induced sensitive area. TAISAM circuits were irradiated under the heavy ions. The measured sensitive areas are 1.75 μm2 and 1.00 μm2 with different LET values. TAISAM circuits are also used to investigate the layout structures that can affect the sensitive area. When the source region of the target transistor is floating, the heavy ion-induced sensitive area decreases by 28.5% for the target PMOS transistor while it increases by more than 28% for the target NMOS transistor. When the well contacts are added, the heavy ion-induced sensitive area decreases by more than 25% for the target PMOS transistor while it remains unchanged for the target NMOS transistor. Experimental results directly validate that the two structures significantly affect the heavy ion-induced sensitive area.

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The Separation Measurement of $P$ -Hit and $N$ -Hit Charge Sharing With an “S-Like” Inverter Chains Test Structure

Cited by 10 publications

References 20 publications

Bulk Bias as an Analog Single-Event Transient Mitigation Technique with Negligible Penalty

Bulk Bias as an Analog Single-Event Transient Mitigation Technique with Negligible Penalty

A dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination

TAISAM: A Transistor Array-Based Test Method for Characterizing Heavy Ion-Induced Sensitive Areas in Semiconductor Materials

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