TAISAM: A Transistor Array-Based Test Method for Characterizing Heavy Ion-Induced Sensitive Areas in Semiconductor Materials

Abstract

The heavy ion-induced sensitive area is an essential parameter for space application integrated circuits. Circuit Designers need it to evaluate and mitigate heavy ion-induced soft errors. However, it is hard to measure this parameter due to the lack of test structures and methods. In this paper, a test method called TAISAM was proposed to measure the heavy ion-induced sensitive area. TAISAM circuits were irradiated under the heavy ions. The measured sensitive areas are 1.75 μm2 and 1.00 μm2 with different LET values. TAISAM circuits are also used to investigate the layout structures that can affect the sensitive area. When the source region of the target transistor is floating, the heavy ion-induced sensitive area decreases by 28.5% for the target PMOS transistor while it increases by more than 28% for the target NMOS transistor. When the well contacts are added, the heavy ion-induced sensitive area decreases by more than 25% for the target PMOS transistor while it remains unchanged for the target NMOS transistor. Experimental results directly validate that the two structures significantly affect the heavy ion-induced sensitive area.

Machine Learning-Based Soft-Error-Rate Evaluation for Large-Scale Integrated Circuits

“…Some ions strike the test chips and generate transient pulses. The test system consisted of a test chip and other necessary chips, such as field-programmable gate arrays (FPGAs) and serial communication chips [29,30]. FPGAs connected all signal ports (input, output, and clock) of the test chip to provide input and clock signals.…”

Radiation-Tolerant Electronics

“…Two articles in this issue deal more with the fundamental effects of radiation in semiconductor materials and advanced IC technologies. In [11], the authors present a transistor-array-based test method for characterizing the heavy-ion-induced sensitive area in semiconductor materials as well as the impact of transistor layout and well contacts for both NMOS and PMOS devices in 65 nm CMOS technology. Article [12] presents a comparison of TID effects in 22 nm and 28 nm FDSOI (fully depleted silicon-on-insulator) technologies.…”