Bulk Bias as an Analog Single-Event Transient Mitigation Technique with Negligible Penalty

Semicond. Sci. Technol.

Sun

et al. 2020

Self Cite

In nanometer bulk CMOS processes, multi-node charge collection induced by a heavy-ion strike is prevalent. Pulse quenching caused by charge sharing between the struck node (termed as active device) and the following gate (termed as passive device) has been widely studied in digital circuits. This paper firstly demonstrates that the pulse quenching effect also exists between the adjacent stages of analog circuits and can be used to mitigate analog single-event transient (ASET) perturbation. Contrary to digital circuits, whose propagated SET is minimized with the charge collected by passive device maximized, simulation results indicate that there is an optimal spacing between the active and passive devices in analog circuits. When the spacing is too close, the SET induced by the hit node is efficiently mitigated by pulse quenching effect, but the disturbance caused by the charge sharing collection in passive device becomes dominant. Simulation results show that pulse quenching effect has a dual role in ASET mitigation. This paper provides innovative guidance to the radiation-hardening design for analog circuits.

Section: Discussionmentioning

confidence: 99%

Pulse quenching based radiation-hardened by design technique for analog single-event transient mitigation on an operational amplifier in 28 nm bulk CMOS process

Semicond. Sci. Technol.

Sun

et al. 2020

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“…We simulated an ion strike at the center of drain of a normal transistor. As in our previous works [15][16][17][18][19], advanced physical models and robust numeric methods are incorporated for the SET simulation, and the following physical models are included: (a) Fermi-Dirac statistics, (b) a doping-dependent carrier mobility model with high electric field saturation, carrier-carrier scattering, and interface scattering; (c) a carrier recombination model: doping dependent SRH and Auger recombination; (d) the effect of band-gap narrowing; (e) a hydrodynamic carrier transport model. Unless otherwise specified, default physical models and parameters are provided by the Sentaurus TCAD.…”

Section: Simulation Detailsmentioning

confidence: 56%

Current mirror featuring DTMOS for analog single‐event transient mitigation in space application

Semicond. Sci. Technol.

Sun

et al. 2020

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Dynamic threshold-voltage MOSFETs (DTMOSs) with bulk and gate tied together are commonly used in ultra-low voltage applications. Since the threshold voltage of the device is a function of its gate voltage, and the current-driving capability is boosted as the gate-source voltage increases, it has the potential to be applied in the community of radiation-hardened IC circuits. This paper firstly demonstrates that DTMOS is particularly suitable for analog single-event transient (ASET) mitigation in cascode current mirrors with negligible penalty. A basic current mirror and a cascode current mirror are modelled to analyze the devices in DTMOS configuration, and compare radiation performance with standard MOSFETs. Simulation results demonstrate that the DTMOS scheme reduces charge collection, and suppresses single-event effect-induced perturbation effectively in the cascode current mirror, while playing a detrimental role in basic current mirrors due to the well-known bipolar effect. This technique provides a novel method for mitigating ASET disturbances for the designers of spaceborne ICs.

“…By enlarging the transistor size, the drive capability is increased, and heavy‐ion‐induced charges can be dissipated more rapidly [7]. A similar technique is forward biasing the bulk of vulnerable transistor, which decreases the threshold voltage and increases the device drivability [8,9]. Another mitigation technique is lowering impedance at critical nodes, which enhances the escape speed of the excess ionization charges toward supply rails [10,11].…”

Section: Rhbd Current Mirror Circuitsmentioning

confidence: 99%

Current mirror with charge dissipation transistor for analogue single‐event transient mitigation in space application

IET Circuits, Devices & Syst

Liang

Chen

et al. 2021

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Current mirror utilizing an extra transistor for single‐event‐induced charge dissipation is proposed. This technique involves two inverters and a dissipation transistor. The inverters are employed as a sensor that turns on the dissipation transistor when heavy ion hits the sensitive node, and the dissipation transistor helps to attenuate the single‐event transient (SET)‐induced perturbation. During normal operation, inverters are in static state, and the dissipation transistor is off, which has no effect on circuit performance, and contributes to negligible power consumption. Once heavy ion strikes the sensitive node and the fault is detected, the dissipation transistor is triggered to self‐correct the SET disturbance. Simulation results indicate that the proposed technique reduces the SET pulse duration by at least 48.4% with linear energy transfers of 30 MeV cm2/mg. This paper provides a novel hardening method for analogue single‐event transient mitigation in current mirror circuits.