Pulse quenching based radiation-hardened by design technique for analog single-event transient mitigation on an operational amplifier in 28 nm bulk CMOS process

Abstract

In nanometer bulk CMOS processes, multi-node charge collection induced by a heavy-ion strike is prevalent. Pulse quenching caused by charge sharing between the struck node (termed as active device) and the following gate (termed as passive device) has been widely studied in digital circuits. This paper firstly demonstrates that the pulse quenching effect also exists between the adjacent stages of analog circuits and can be used to mitigate analog single-event transient (ASET) perturbation. Contrary to digital circuits, whose propagated SET is minimized with the charge collected by passive device maximized, simulation results indicate that there is an optimal spacing between the active and passive devices in analog circuits. When the spacing is too close, the SET induced by the hit node is efficiently mitigated by pulse quenching effect, but the disturbance caused by the charge sharing collection in passive device becomes dominant. Simulation results show that pulse quenching effect has a dual role in ASET mitigation. This paper provides innovative guidance to the radiation-hardening design for analog circuits.

A system-level method for hardening phase-locked loop to single-event effects

“…Besides, the unlock due to SEEs can be mitigated by radiation-hardened layout rules that optimize the space between N-type and P-type active areas, the space between active areas and substrate contacts, and so on. Those rules were followed in our previous works and also verified [4,11,19].…”

“…A common circuit model for simulating the single-event effects is a double-exponential, time-dependent current pulse [19][20][21]. This pulse can be given by:…”

Current mirror with charge dissipation transistor for analogue single‐event transient mitigation in space application

“…To verify the effectiveness of the proposed technique, 3D TCAD simulation tool is adopted in this work. TCAD has been proven to be a useful tool for SET investigation, which provides insight into the physical mechanisms of SEEs [13,14].…”

“…As a result, the SET pulse width is modified as follows, which is alleviated attributed to the dissipation current (I d ) through the pull-down transistor M d : To verify the effectiveness of the proposed technique, 3D TCAD simulation tool is adopted in this work. TCAD has been proven to be a useful tool for SET investigation, which provides insight into the physical mechanisms of SEEs [13,14].…”

Comparison of single event effect on cascoded low noise amplifier performance metrics for two different frequencies

“…In the literature, the SEE problem has been reported in many combinational circuits as well as sequential circuits [3][4][5][6][7]. The SET investigation has been discussed in analog and digital circuits such as operational amplifiers, SRAM, power converters, feedback amplifiers, and comparators [8][9][10][11][12]. In order to compete with other technological rivals like high-electron mobility transistors (HEMT), Si-Ge, Bi-CMOS, and III-IV technology, RF CMOS technology now has the capability to drive gigahertz-range applications thanks to a new scaling trend.…”