Current mirror with charge dissipation transistor for analogue single‐event transient mitigation in space application

Abstract

Current mirror utilizing an extra transistor for single‐event‐induced charge dissipation is proposed. This technique involves two inverters and a dissipation transistor. The inverters are employed as a sensor that turns on the dissipation transistor when heavy ion hits the sensitive node, and the dissipation transistor helps to attenuate the single‐event transient (SET)‐induced perturbation. During normal operation, inverters are in static state, and the dissipation transistor is off, which has no effect on circuit performance, and contributes to negligible power consumption. Once heavy ion strikes the sensitive node and the fault is detected, the dissipation transistor is triggered to self‐correct the SET disturbance. Simulation results indicate that the proposed technique reduces the SET pulse duration by at least 48.4% with linear energy transfers of 30 MeV cm2/mg. This paper provides a novel hardening method for analogue single‐event transient mitigation in current mirror circuits.