A Body-Biasing Technique for Single-Event Transient Mitigation in 28-nm Bulk CMOS Process

Liu, Jingtian; Liang, Bin; Guo, Yang; Chen, Jianjun; Chi, Yaqing; Sun, Quan; Song, Shengyu; Yuan, Hengzhou

doi:10.1109/tns.2021.3123335

Cited by 3 publications

(1 citation statement)

References 24 publications

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“…7,8) Layout-based radiation hardening techniques can alleviate the single-event effect to some extent for both N-type metal-oxide-semiconductor (NMOS) and P-type metal-oxide-semiconductor (PMOS). [9][10][11] Some reported work has shown that the transistor stacking causes a SET cross-section reduction of about 66.3% at 2.5 MeV•cm 2 mg −1 for the NOR logic gate, 12) and 18.6% reduction of SET pulse width is obtained in inverter by adjusting the NMOS transistor placement. 13) Although the hardened designs decrease the effects of SET on standard cells, the results mainly reflect an average level.…”

Section: Introductionmentioning

confidence: 99%

Investigation of PVT variation on single-event transient effect assisted with hardened layout techniques

Liang¹,

Luo²,

Sun³

et al. 2022

Jpn. J. Appl. Phys.

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With the aggressively scaled technology, the single-event transient (SET) in the integrated circuits is regarded as one of the critical threats to the system reliability, where the hardening efficiency strongly depends on the randomness of striking positions and process-voltage-temperature (PVT) variations. To enhance the SET robustness and improve the immunity to PVT variations, different layout-based hardening techniques are proposed and compared. Moreover, the tolerance of PVT for hardened layouts and the underlying physics reasons are investigated by technology-computer-aided-design (TCAD) simulations. The simulation reveals that the techniques combining the split active area (SAA), gapless well and source (GWS), and the selectively implanted deep N-well (SIDNW) enable to reduce the transient pulse width as well as mitigate the variations from PVT and hit position.

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