2022
DOI: 10.1088/2053-1591/ac8f87
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A system-level method for hardening phase-locked loop to single-event effects

Abstract: To mitigate the sensitivity of the charge pump in a traditional Phase-Locked Loop(PLL), a single-event-hardened PLL architecture with a proportional and integral path is proposed. The phase margin of the PLL is kept at 58.16° due to the rational design and the output clock frequency ranges from 0.8 to 3.2 GHz. The circuit-level simulation results reveal that the sensitive volume of the hardened PLL decreases by 80% ~ 95%. The novel radiation-hardened PLL circuit was implemented in a 28 nm CMOS technology and i… Show more

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Cited by 5 publications
(4 citation statements)
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References 22 publications
(24 reference statements)
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“…It simplifes the design of the checker processor by incorporating shared branch prediction, instruction prefetching, and other structures. In addition to redundancy computing methods, there is another class of system-level reinforcement methods known as online supervision methods, including control fow detection and watchdogs [67].…”
Section: System-levelmentioning
confidence: 99%
“…It simplifes the design of the checker processor by incorporating shared branch prediction, instruction prefetching, and other structures. In addition to redundancy computing methods, there is another class of system-level reinforcement methods known as online supervision methods, including control fow detection and watchdogs [67].…”
Section: System-levelmentioning
confidence: 99%
“…It is often used to achieve frequency synthesis, clock generation, clock recovery, and other functions [18]. Figure 2 shows the topological structure of the charge pump phase-locked loop (CPPLL), which is mainly composed of five submodules, namely, the frequency discriminator (PFD), the charge pump (CP), the low-pass In recent years, in order to reduce the effect of the SET on a PLL, researchers have proposed various methods to reduce the SET sensitivity of the CP output stage [2,[13][14][15][16][17]. Loveless et al [15] proposed that the hardened scheme of changing the current-type CP to the voltage-type CP could effectively reduce the SET sensitivity.…”
Section: Topology Of the Cppllmentioning
confidence: 99%
“…In order to improve the ability of the VCO to resist the single-event effect, many researchers have proposed effective VCO-hardened structures [12][13][14][15][16][17][18][19]. H. Yuan et al reduced the sensitivity of the VCO to bias through multi-bias technology and interleaving bias [12], while the ability of the single-event transient effect tolerance of the ring oscillator was improved through layout hardening.…”
Section: Introductionmentioning
confidence: 99%
“…However, this digital coding reinforcement scheme would introduce additional sensitive nodes in digital circuits. B. Liang et al proposed a proportional and integral path-independent PLL-hardened scheme [18], and simulation results showed that the frequency error caused by radiation on the VCO was reduced by 80% to 90%. V. Diez-Acereda and others used a filter network to harden the oscillator [19], and introduced an RC network to suppress current transients, thus improving the ability of the VCO to resist the SET effect.…”
Section: Introductionmentioning
confidence: 99%