Current mirror featuring DTMOS for analog single‐event transient mitigation in space application

Abstract

Dynamic threshold-voltage MOSFETs (DTMOSs) with bulk and gate tied together are commonly used in ultra-low voltage applications. Since the threshold voltage of the device is a function of its gate voltage, and the current-driving capability is boosted as the gate-source voltage increases, it has the potential to be applied in the community of radiation-hardened IC circuits. This paper firstly demonstrates that DTMOS is particularly suitable for analog single-event transient (ASET) mitigation in cascode current mirrors with negligible penalty. A basic current mirror and a cascode current mirror are modelled to analyze the devices in DTMOS configuration, and compare radiation performance with standard MOSFETs. Simulation results demonstrate that the DTMOS scheme reduces charge collection, and suppresses single-event effect-induced perturbation effectively in the cascode current mirror, while playing a detrimental role in basic current mirrors due to the well-known bipolar effect. This technique provides a novel method for mitigating ASET disturbances for the designers of spaceborne ICs.

A system-level method for hardening phase-locked loop to single-event effects

“…A common circuit model for simulating the single-event effects is a double-exponential, time-dependent current pulse [19][20][21]. This pulse can be given by:…”

Current mirror with charge dissipation transistor for analogue single‐event transient mitigation in space application

“…We simulated ion strike at the centre of drain of the struck transistor normally. Same as our previous works [16–18], the included physical models are (a) Fermi–Dirac statistics; (b) the doping‐dependent carrier mobility model with high electric field saturation, carrier–carrier scattering, as well as interface scattering; (c) carrier recombination model: doping‐dependent SRH and Auger recombination; (d) the effect of band‐gap narrowing; (e) hydrodynamic carrier transport model; (f) other models are configured with default models and parameters.…”

“…We simulated ion strike at the centre of drain of the struck transistor normally. Same as our previous works [16][17][18] Ideally, current mirrors should be invariant over operating conditions. In order to prove the circuits' robustness, SPICE simulations are carried out for process, voltage supply, and temperature (PVT) analysis at the bias point of 50 μA.…”