The RD53 collaboration's SystemVerilog-UVM simulation framework and its general applicability to design of advanced pixel readout chips

Abstract

The foreseen Phase 2 pixel upgrades at the LHC have very challenging requirements for the design of hybrid pixel readout chips. A versatile pixel simulation platform is as an essential development tool for the design, verification and optimization of both the system architecture and the pixel chip building blocks (Intellectual Properties, IPs). This work is focused on the implemented simulation and verification environment named VEPIX53, built using the SystemVerilog language and the Universal Verification Methodology (UVM) class library in the framework of the RD53 Collaboration. The environment supports pixel chips at different levels of description: its reusable components feature the generation of different classes of parameterized input hits to the pixel matrix, monitoring of pixel chip inputs and outputs, conformity checks between predicted and actual outputs and collection of statistics on system performance. The environment has been tested performing a study of shared architectures of the trigger latency buffering section of pixel chips. A fully shared architecture and a distributed one have been described at behavioral level and simulated; the resulting memory occupancy statistics and hit loss rates have subsequently been compared.

RD53A: a large scale prototype for HL-LHC silicon pixel detector phase 2 upgrades

“…Lastly, the padframe includes also the Shunt-LDO developed for serial powering. In addition, a UVM-based simulation and verification environment, named VEPIX53, has been developed within the collaboration [3]. This tool, containing automated verification features, has allowed to perform an extensive comparison between the DBA and CBA architectures and mixed signal tests between analog and digital building blocks.…”

CHIPIX65: Developments on a new generation pixel readout ASIC in CMOS 65 nm for HEP experiments

“…A first version of a SystemVerilog-UVM Simulation Framework (VEPIX53) has been made available to the RD53 community [10], [11]. As reported on the block diagram in Figure 10 , the environment is divided in three main parts: i) a top module, which contains the Design Under Test (DUT) and hooks it with the rest of the environment through interfaces in order to build a layered test structure; ii) a testbench, which includes all the UVM Verification Components (UVCs), inherited from the UVM class library; iii) a test scenario portion which defines the configuration of the UVCs and describes the tests that are performed during simulations by specifying the constraints to the input stimuli to be sent to the DUT.…”

RD53 Collaboration and CHIPIX65 Project for the development of an innovative Pixel Front End Chip for HL-LHC

“…The design of several IPblocks are foreseen by RD53 and about one third of them are under the responsibility of CHIPIX65 like DAC and ADC (Bari), BandGap (Pavia, Bergamo), sLVDS-to-CMOS and CMOS-to-sLVDS transceivers (Pavia, Bergamo, Pisa, Torino), rad-hard by design memories like Dice SRAM [8] and logic (Milano), High Speed Serializer/Deserialiser (Pisa) and others like PLL are under discussion in within the RD53 and CHIPIX65. Under the study and definition of the digital architecture Perugia is mainly involved in using high-level modeling tools (SystemVerilog) in order to collect sufficient statistic on the actual performance of the system in very high rate, high energy physics experiments [9,10]. The study of Input protocols to receive clock and trigger signals and commands to the chip is done by Pisa looking to data protection from SEU events using Hamming encoding or other options, while Bari is concerned in providing monitoring data from the chip.…”