The minimum noise figure and mechanism as scaling RF MOSFETs from 0.18 to 0.13 μm technology nodes

RF Power Performance of Asymmetric-LDD MOS Transistor for RF-CMOS SOC Design

“…The devices we studied in this work are multiple fingers MOS transistors with 10 gate fingers, 0.23-m gate length and 5 m width. For comparison, the same interconnect and RF layout were used [6]- [10]. The devices were fabricated by a standard logic process provided by IC foundry.…”

“…Besides the advantages on digital performance, the scaling of CMOS technology also has largely improved the radio frequency (RF) performance of MOS devices. The most significant improvement along with CMOS technology scaling is the larger RF gain, higher cut-off frequency , and maximum oscillation frequency [1]- [10]. This has made CMOS device technology the prime choice for RF system-onchip (SoC) application such as WCDMA, W-LAN, and ultrawide band (UWB) wireless communication.…”

DC-RF Performance Improvement for Strained 0.13 μm MOSFETs mounted on a Flexible Plastic Substrate

“…Multiple-gate-finger (8, 16, and 32) 0.13 tm MOSFETs [6]- [8] with a novel microstrip line layout [2]- [4] were used in this study. The multiple-gate-finger structure was used to reduce the gate-resistance-generated thermal noise and the microstrip line layouts were designed using Metal-I as the ground plane to reduce the RF noise from the lossy Si substrate [3].…”

“…The device characteristics were measured using an HP4 1 55C for DC, HP85 1 OC network analyzer for S-parameter and ATN-NP5B for noise measurements [6]- [8]. Figure 2 shows a comparison of DC Id -Vg and Id -Vd characteristics for the 16-gate-finger n-MOSFET on a VLSIstandard substrate and on plastic with the 40 tm Si.…”

RFIC TaN/SrTiO$_3/$TaN MIM Capacitors With 35fF$/muhboxm^2$Capacitance Density

“…However, such crystallization is needed for STO to give a much higher value than amorphous HfO and TaTiO [10]. For a typical large 1-pF capacitor used in RF IC, a very small leakage current of only 29 fA is obtained due to the very high value, which is much smaller than the off-state current of a MOSFET with deep sub-100 nm gate length [12], [13]. Fig.…”