The Lowest On-Resistance and Robust 130nm BCDMOS Technology implementation utilizing HFP and DPN for mobile PMIC applications

Kim, Daehoon; Lee, Kuemju; Kim, Jaeeuk; Jung-Hun, Choi; Lee, Jaehee; Cho, Inwook

doi:10.1109/ispsd.2019.8757571

Cited by 12 publications

(6 citation statements)

References 3 publications

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“…From the comparison with Kim et al [6], it can be seen that our device owns a better (or called larger) SOA region, which is also an indication of the robustness of the optimized process condition.…”

Section: Electrical Resultsmentioning

confidence: 55%

“…Step (6) Light doping drain module, then oxide-Si 3 N 4 -oxide spacer, source/drain engineering process. Step (7) Back end of the line connection with AlCu metal.…”

Section: Methodsmentioning

confidence: 99%

“…There are also many research works about novel structures, including surrounded stress dielectric layer LDMOS [2], folded accumulation LDMOS [5], optimized high-temperature oxide field plate, and the decoupled plasma nitridation LDMOS [6], H-shape shallow-trench isolation (STI) field plate LDMOS [7], or even silicon-on-insulator LDMOS [8], and high breakdown voltage devices with new material Ga 2 O 3 [9]. These papers provided certain innovative device structures with encouraged R on,sp or BV ds,max performance by simulation results or small amounts of electrical results.…”

Section: Introductionmentioning

confidence: 99%

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A Process Optimization Method of the Mini-LOCOS Field Plate Profile for Improving Electrical Characteristics of LDMOS Device

Yu,

Shao,

Gao

et al. 2023

IET Circuits, Devices & Systems

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In this work, the effects of the mini-local oxidation of silicon (LOCOS) field plate’s bottom physical profile on the devices’ breakdown performance are analyzed through technology computer-aided design simulations. It is indicated that the “abrupt” bottom profile could certainly do with an optimization. This paper introduces an effective process improvement method by etching bias power adjustment and time reduction. The upgradation of the field plate physical profile has been proved by transmission electron microscope cross-section analysis. The angle for the bottom surface of mini-LOCOS field plate θ2 is improved from 11.9° to 12.6°, and the thickness ratio of Hup/Hbottom (field plate oxide thickness for the upper and bottom, respectively) is increased from 71.8% to 76.6%. Finally, the optimized laterally diffused metal oxide semiconductor devices have been fabricated, and both figure of merit curves and safe operation area curves are measured. The specific on-resistance Ron,sp could achieve as low as 11.3 mΩ mm2, while breakdown voltage BVds,max arrives at 37.4 V, which is nearly 19.3% improved.

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Section: Electrical Resultsmentioning

confidence: 55%

“…Step (6) Light doping drain module, then oxide-Si 3 N 4 -oxide spacer, source/drain engineering process. Step (7) Back end of the line connection with AlCu metal.…”

Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Process Optimization Method of the Mini-LOCOS Field Plate Profile for Improving Electrical Characteristics of LDMOS Device

Yu,

Shao,

Gao

et al. 2023

IET Circuits, Devices & Systems

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“…Fig. 7 compares the FOM determined in this work for LDMOS transistors with Baliga's FOM for an ideal drift region, our TCAD results, and recent lateral transistors with new technologies and designs [38]- [44]. The solid black line shows our proposed FOM derived from Eq.…”

Section: Numerical Verificationmentioning

confidence: 81%

LDMOS Drift Region With Field Oxides: Figure-of-Merit Derivation and Verification

Saadat

Put

Edwards

et al. 2022

IEEE J. Electron Devices Soc.

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We analytically and numerically investigate the performance of Laterally-Diffused Metal-Oxide-Semiconductor (LDMOS) transistors with Semi-circular Field OXide (S-FOX) focusing on midvoltage (30 V -100 V) power applications. We derive an analytical relation between breakdown voltage and on-resistance to realize the ideal behavior of the drift region for an LDMOS with S-FOX. Then, we find the optimized drift doping concentration minimizing the on-resistance at a given breakdown voltage. We introduce a new figure-of-merit for the drift region of a lateral device with S-FOX. We finally verify our ideal analytical findings with numerical results modeled and simulated in a commercial Technology Computer-Aided Design (TCAD).

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“…Laterally diffused metal-oxide semiconductor (LDMOS) field-effect transistors (FETs) are commonly used for lowvoltage (< 30 V) [1][2][3][4], mid-voltage (30 V -100 V) [5][6][7], and high-voltage (> 100 V) [8,9] power applications. Many novel LDMOS device technologies with different device configurations have been proposed recently to achieve a better figure-of-merit (FOM = BV 2 /Ron), i.e., a high breakdown voltage (BV) with a low on-resistance (Ron), for different practical voltage ranges [10][11][12][13][14]. However, complex device structures are often introduced in these proposed technologies which make the industrial fabrication process very difficult and costly.…”

Section: Introductionmentioning

confidence: 99%

Channel Length Optimization for Planar LDMOS Field-Effect Transistors for Low-Voltage Power Applications

Saadat

Put

Edwards

et al. 2020

IEEE J. Electron Devices Soc.

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We identify an optimum channel length for planar Laterally Diffused Metal-Oxide-Semiconductor (LDMOS) field-effect transistors, in terms of the specific on-resistance, through systematic device simulation and optimization. We simulate LDMOS devices with different channel lengths ranging from 100 nm to 10 nm, modifying the length of the drift region and doping concentration of the body region to match a predetermined leakage current suitable for lowvoltage power applications (3.3V and 5V). For devices with a channel length exceeding 40 nm, reducing the channel length decreases the onresistance as expected. Below 40 nm, an increase in resistance is observed as the result of an increased body doping concentration leading to significant electron mobility degradation in the channel area.

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The Lowest On-Resistance and Robust 130nm BCDMOS Technology implementation utilizing HFP and DPN for mobile PMIC applications

Cited by 12 publications

References 3 publications

A Process Optimization Method of the Mini-LOCOS Field Plate Profile for Improving Electrical Characteristics of LDMOS Device

A Process Optimization Method of the Mini-LOCOS Field Plate Profile for Improving Electrical Characteristics of LDMOS Device

LDMOS Drift Region With Field Oxides: Figure-of-Merit Derivation and Verification

Channel Length Optimization for Planar LDMOS Field-Effect Transistors for Low-Voltage Power Applications

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