The influence of fluorine on threshold voltage instabilities in p/sup +/ polysilicon gated p-channel MOSFETs

Baker, F.K.; Pfiester, J.R.; Mele, T.C.; Tseng, Hsing‐Huang; Tobin, Philip J.; Hayden, J.D.; Gunderson, C.D.; Parrillo, L.C.

doi:10.1109/iedm.1989.74317

Cited by 29 publications

(10 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Also the boron penetration induced negative oxide charge generation can be reduced [7], [18], as shown in Fig. 2(b dielectric breakdown field [5], [15]. Fig.…”

Section: B Electrical Characteristics Of the P+ Sas And Adp Gate Capmentioning

confidence: 76%

“…The BF2 implantation is typically used to form the p+ poly-Si gate as well as the shallow p+-n junction [5]. Unfortunately, the F-incorporated p+ poly-Si gate can not only enhance the boron penetration through the thin gate oxide into the Si substrate but also cause the generation of negative-charge interface states [5]- [8]. This results in a large threshold voltage shift, a large charge trapping rate and a poor reliability of device [5]- [8].…”

Section: Introductionmentioning

confidence: 99%

“…Unfortunately, the F-incorporated p+ poly-Si gate can not only enhance the boron penetration through the thin gate oxide into the Si substrate but also cause the generation of negative-charge interface states [5]- [8]. This results in a large threshold voltage shift, a large charge trapping rate and a poor reliability of device [5]- [8]. It has also indicated that the more fluorine atoms pile up at the poly-Si/SiO2 and Si/SiO2 interfaces, the more serious the boron penetration occurs [9].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Suppression of the boron penetration induced dielectric degradation by using a stacked-amorphous-silicon film as the gate structure for pMOSFET

Lee

Lei

1996

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

This work proposes a stacked-amorphous-silicon (SAS) film as the gate structure of the p+ poly-Si gate pMOSFET to suppress boron penetration into the thin gate oxide. Due to the stacked structure, a large amount of boron and fluorine piled up at the stacked-Si layer boundaries and at the poly-SilSiO2 interface during the annealing process, thus the penetration of boron and fluorine into the thin gate oxide is greatly reduced. Although the grain size of the SAS film is smaller than that of the as deposited polysilicon (ADP) film, the boron penetration can be suppressed even when the annealing temperature is higher than 950°C. In addition, the mobile ion contamination can be significantly reduced by using this SAS gate structure. This results in the SAS gate capacitor having a smaller flat-band voltage shift, a less charge trapping and interface state generation rate, and a larger charge-to-breakdown than the ADP gate capacitor. Also the Si/SiOz interface of the p+ SAS gate capacitor is much smoother than that of the p+ SAS gate capacitor.

show abstract

“…Also the boron penetration induced negative oxide charge generation can be reduced [7], [18], as shown in Fig. 2(b dielectric breakdown field [5], [15]. Fig.…”

Section: B Electrical Characteristics Of the P+ Sas And Adp Gate Capmentioning

confidence: 76%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Suppression of the boron penetration induced dielectric degradation by using a stacked-amorphous-silicon film as the gate structure for pMOSFET

Lee

Lei

1996

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

show abstract

“…Boron penetration into the oxide or the channel is therefore a major concern for deep sub-micron CMOS technology [1,2] particularly with the thermal budgets and ultra-thin gate dielectrics required in today's CMOS processes. The addition of fluorine, introduced by implantation with BF 2 , or exposure to hydrogen containing ambients is shown to accelerate the rate of boron diffusion through thin gate dielectrics [3,4,5]. Dielectric thickness scaling is also demonstrated to result in a rapid increase in the level of boron penetration for a given set of thermal process conditions.…”

Section: Introductionmentioning

confidence: 98%

Nitric Oxide Rapid Thermal Nitridation of Thin Gate Oxides

et al. 1997

View full text Add to dashboard Cite

Nitric oxide rapid thermal nitridation of thin gate oxides was investigated. Oxides from 25 to 55 A were grown in 02 and subsequently nitrided in a nitric oxide (NO) ambient using an Applied Materials RTP Centura chamber. Nitrogen incorporation and film thickness growth during NO nitridation were evaluated. Peak nitrogen incorporation was most strongly influenced by temperature and time, with moderate influence by initial oxide thickness, and no significant influence due to NO flow rate. Peak nitrogen concentrations ranged from 1 to 9 atomic percent as characterized by Secondary Ion Mass Spectrometry (SIMS) analysis. Oxide growth during nitridation ranged from 2 A to II A with no degradation in uniformity. These data were used in the design of two 40 A oxynitride processes incorporating 2 and 4 peak atomic percent nitrogen. High quality MOS capacitors were demonstrated with these dielectrics. Performance was compared against a baseline furnace process as well as non-nitrided RTO. Throughout this work, the chamber integrity was monitored using visual inspection, minority carrier lifetime (MCLT) and surface photovoltage (SPV). No contamination, corrosion or other degradation of the process chamber was observed in over 6 months' operation with over 700 NO processes completed. The controllability, uniformity and high nitrogen incorporation of rapid thermal NO nitridation make it an attractive process for deep sub-micron gate insulators.

show abstract

“…An increase in boron penetration is also observed in the presence of fluorine, e.g., when gate, source, and drain are simultaneously implanted with BF, [9,IO]. An increase in the oxide trap density is attributed to the presence of boron which is believed to enhance the retention of water in the oxide [ I I].…”

Section: Introductionmentioning

confidence: 99%

Design of submicron PMOSFETs for DRAM array applications

El-Kareh

Abadeer

Tonti

International Electron Devices Meeting 1991 [Technical Digest]

View full text Add to dashboard Cite

A comparison is made between surface-channel P+ polysilicon gate and buried-channel N+ polysilicon gate PMOSFETs used as switching devices in DRAM arrays in a 3.3 V CMOS technology. The criterion for this comparison is the "end-of-life" magnitude of subthreshold off-current at zero gate-to-source voltage, projected from accelerated hot-carrier stress. Shifts in off-current depend on changes in threshold voltage and subthreshold slope. The minimum channel length which satisfies the lifetime criterion of 100% shift in off-current for surface channels is 0.3 pm. The minimum channel length of buried channels must be increased by 4 . 2 5 p m over that of surface channels to meet the same lifetime criterion. This results in a reduction in drain current of N 30%.

show abstract

The influence of fluorine on threshold voltage instabilities in p/sup +/ polysilicon gated p-channel MOSFETs

Cited by 29 publications

References 7 publications

Suppression of the boron penetration induced dielectric degradation by using a stacked-amorphous-silicon film as the gate structure for pMOSFET

Suppression of the boron penetration induced dielectric degradation by using a stacked-amorphous-silicon film as the gate structure for pMOSFET

Nitric Oxide Rapid Thermal Nitridation of Thin Gate Oxides

Design of submicron PMOSFETs for DRAM array applications

Contact Info

Product

Resources

About