Design of submicron PMOSFETs for DRAM array applications

Abstract

A comparison is made between surface-channel P+ polysilicon gate and buried-channel N+ polysilicon gate PMOSFETs used as switching devices in DRAM arrays in a 3.3 V CMOS technology. The criterion for this comparison is the "end-of-life" magnitude of subthreshold off-current at zero gate-to-source voltage, projected from accelerated hot-carrier stress. Shifts in off-current depend on changes in threshold voltage and subthreshold slope. The minimum channel length which satisfies the lifetime criterion of 100% shift in off-current for surface channels is 0.3 pm. The minimum channel length of buried channels must be increased by 4 . 2 5 p m over that of surface channels to meet the same lifetime criterion. This results in a reduction in drain current of N 30%.

A test structure to separately analyze CMOSFET reliabilities around center and edge along the channel width

“…It is expected that the STI technology may modulate the high electric fields near the channelwidth edge resulting in the reliability variation along the channel-width direction, because the narrow-width or the inverse-narrow-width effects are largely influenced by the STI process [7,8]. Until now, the reliability comparison between the buried-and the surface-channel narrow-width p-MOSFETs fabricated by STI was reported [9]. Furthermore, the channelwidth dependences of the hot-carrier induced degradation have been studied for n-MOSFETs [6] and SOI n-MOSFETs [10], in which the narrow-width devices had inferior reliability due to the accelerated hot-carrier generation and the injection rates at the channel-region adjacent to the STI edge, and due to the lower gate-oxide-breakdown caused by the large edge current after the hot-carrier stressing around the channel-edge region, respectively.…”