The IBM z13 multithreaded microprocessor

Abstract

The IBM z13i system is the latest generation of the IBM z Systemsi mainframes. The z13 microprocessor improves upon the IBM zEnterprise A EC12 (zEC12) processor with two vector execution units, higher instruction execution parallelism, and a simultaneous multithreaded (SMT) architecture that supports concurrent execution of two threads. These advances yield performance gains in legacy online transaction processing and business analytics workloads. This latest generation system features an eight-core processor chip, a robust cache hierarchy, and large multiprocessor system design optimized for enterprise database and transaction processing workloads. The microprocessor core features a wide super-scalar, out-of-order pipeline that can sustain an instruction fetch, decode, dispatch, and completion rate of six z/Architecture A instructions per cycle. The instruction execution path is predicted by multi-level branch direction and target prediction logic. Complex instructions are split into two or more simpler micro-operations. Instructions are issued out of program order from an instruction issue queue to multiple RISC (reduced instruction set computer) execution units. The super-scalar design can sustain an issue and execution rate of ten micro-operations per cycle: two load/store type instructions, four fixed point (integer) instructions, two floating point or vector instructions, and two branch instructions.

IBM z13 circuit design and methodology

“…analytics workloads, SMT (simultaneous multithreading) support, and additional logic for increased performance in branch prediction and out-of-order processing [6]. Given the unprecedented size and complexity of the processor core, and both CP and SC chips in general, the circuit design methodology needed to focus on enabling high levels of designer productivity, while simultaneously achieving the challenging chip frequency target.…”

The IBM z13 processor cache subsystem

“…Together, this forms the new system interconnect topology shown to the right in Figure 1, where the system nodes can be arranged in row-column format, on-drawer nodes are referred to as siblings, and off-drawer nodes have near and far interconnections, depending on whether the off-drawer ABus needs to be traversed. Figure 3 highlights the changes in the system cache content, with the private store-through L2 cache [1] size doubling to 4 MB per core, the shared store-in L3 cache increasing to 64 MB [12] shared by 8 processor cores, maintaining the cache bit per core ratio from the zEC12, and the shared store-in L4 system level cache increasing to 480 MB shared among 24 cores, roughly doubling the cache bit-per-core ratio from the zEC12. New to the z13 SC chip is the Non-data Inclusive Coherent (NIC) directory, which works in unison with the L3 and L4 caches to provide node-level, or nodal, coherency The zEC12 processor system.…”

“…It features up to 192 two-way simultaneous multithreaded (SMT2) [1] processors, or cores, operating at 5 GHz, distributed across four fully connected processing drawers. Each drawer consists of two tightly coupled processing nodes, up to 2.5 terabytes (TB) of physical memory, up to 4 legacy Galaxy (GX) I/O adapters, and 10 integrated PCIe** x16 Generation-3 I/O hubs [2], along with an enhanced four-level cache design.…”

Robust power management in the IBM z13

“…For a description of the CP chip microarchitecture, implementation and design methodology details, the reader is referred to other papers in this issue (e.g., [6,7]). The z13 power management architecture is implemented as a two-level hierarchy: core-level and chip-level.…”