The IBM z13 processor cache subsystem

Walters, C. R.; Mak, P.; Berger, D. P. D.; Blake, Michael A.; Bronson, T.; Klapproth, K. D.; O'neill, Arthur; Sonnelitter, Robert; Papazova, V. K.

doi:10.1147/jrd.2015.2428591

Cited by 5 publications

(5 citation statements)

References 13 publications

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“…Like its predecessor systems (e.g., the IBM System z10* Enterprise Class (EC), the z196, and the zEC12), the z13 system design is founded on a CPC design that incorporates four interconnected CPC processor packages. Beyond this, the similarities quickly diverge, such that the traditional four vertical processor unit (PU) "book" and cage design is replaced by four horizontal PU drawers employing a dispersed interconnection scheme to support both drawer-to-drawer and CPC-system communication [4,5].…”

Section: Cpc Designmentioning

confidence: 99%

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Mechanical packaging, power, and cooling design for the IBM z13

et al. 2015

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Section: Cpc Designmentioning

confidence: 99%

“…Departing from previous designs, the CPC drawer design for the z13 now incorporates two processing nodes rather than a single processing node [4]. Each node comprises three single-chip-module (SCM) based processor modules and a single system controller (SC) module [5].…”

Section: Cpc Designmentioning

confidence: 99%

Mechanical packaging, power, and cooling design for the IBM z13

et al. 2015

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“…IBM z15 [9,72,101] and prior system generations [10,11,17,28,50,51,80,95,96] implemented shared physical L3 caches on the processor chip, and had a separate chip that implemented a large L4 cache. The Telum design implements all of that logic in a single chip, and opts to quadruple the L2 cache to 32 MB with very low latency.…”

Section: Introductionmentioning

confidence: 99%

AI accelerator on IBM Telum processor

Lichtenau

Buyuktosunoglu²,

Bertran³

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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IBM Telum is the next generation processor chip for IBM Z and LinuxONE systems. The Telum design is focused on enterprise class workloads and it achieves over 40% per socket performance growth compared to IBM z15. The IBM Telum is the first server-class chip with a dedicated on-chip AI accelerator that enables clients to gain real time insights from their data as it is getting processed.Seamlessly infusing AI in all enterprise workloads is highly desirable to get real business insight on every transaction as well as to improve IT operation, security, and data privacy. While it would undeniably provide significant additional value, its application in practice is often accompanied by hurdles from low throughput if run on-platform to security concerns and inconsistent latency if run off-platform. The IBM Telum chip introduces an on-chip AI accelerator that provides consistent low latency and high throughput (over 200 TFLOPS in 32 chip system) inference capacity usable by all threads. The accelerator is memory coherent and directly connected to the fabric like any other general-purpose core to support low latency inference while meeting the system's transaction rate. A scalable architecture providing transparent access to AI accelerator functions via a non-privileged general-purpose core * This paper is part of the Industry Track of ISCA 2022's program.

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“…The cache and memory topologies were redesigned for higher bandwidth, lower latency, and optimized resourced management. Many of the system and cache improvements are described by Walters et al [3].…”

Section: Introductionmentioning

confidence: 99%

The IBM z13 memory subsystem for big data

et al. 2015

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The IBM z13i system uses the new IBM Centaur memory buffer chip, along with system topology changes, to more than triple system memory capacity (relative to the IBM zEnterprisei EC12) to 10 TB, and more than triple the drawer-level memory bandwidth to 384 GB/s, and double the DIMM (dual in-line memory module) frequency to 1,600 MHz. The z13 eliminates an asynchronous interface for better store protect key performance. The new memory power save feature on the z13 extends the benefit of the IBM customer power save mode and the IBM cycle steering recovery for lower power. The z13 system builds upon the IBM redundant array of independent memory (RAIM), introduced on the IBM z196 system. New reliability features include single-channel memory bus replay, incremental background lane calibration, and memory scrub hard-error management. An innovative fetch and store tagging architecture, along with a memory quiesce engine, is added to detect RAIM asynchronization events and to re-synchronize memory channels for better performance.

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The IBM z13 processor cache subsystem

Cited by 5 publications

References 13 publications

Mechanical packaging, power, and cooling design for the IBM z13

Mechanical packaging, power, and cooling design for the IBM z13

AI accelerator on IBM Telum processor

The IBM z13 memory subsystem for big data

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