IBM z13 circuit design and methodology

Warnock, J.; Berry, Christopher J.; Wood, Michael; Sigal, L.; Mayer, G.; Mayo, M.; Chan, Yuen; Malgioglio, F.; Strevig, Gerald; Nagarajan, Charudhattan; Carey, Seán; Salem, G.; Schroeder, F.; Smith, H.; Phan, D.; Nigaglioni, Ricardo; Strach, Thomas; Ziegler, Matthew M.; Fricke, Niels; Lind, K.; Neves, J.L.; Rangarajan, S. H.; Surprise, Jesse; Isakson, John; Badar, John; Malone, Daniel G.; Plass, D.; Aipperspach, A.; Wendel, D.; Averill, R.M.; Puri, Ruchir

doi:10.1147/jrd.2015.2446871

Cited by 7 publications

(2 citation statements)

References 20 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For a description of the CP chip microarchitecture, implementation and design methodology details, the reader is referred to other papers in this issue (e.g., [6,7]). The z13 power management architecture is implemented as a two-level hierarchy: core-level and chip-level.…”

Section: Power-management Overviewmentioning

confidence: 99%

“…In HW, the pervasive region within the CP/SC (where SC refers to the System Controller) chipset [6] contains a highly optimized microcontroller called the Self-Boot Engine (SBE), so named because the design was first used in the POWER8* microprocessor to assist or replace the "boot" function provided by the flexible service processor (FSP) in Power Systems [10]. The SBE has its own instruction set architecture (ISA) that supports (load/store) instructions that translate to SCOM (scan communications) registers' read/write commands, ALU instructions [e.g., ADD, SUB, AND, OR, XOR, Rotate (left/right)], branch instructions, and others.…”

Section: Power-management Overviewmentioning

confidence: 99%

See 1 more Smart Citation

Robust power management in the IBM z13

et al. 2015

Self Cite

View full text Add to dashboard Cite

The power management strategy adopted for the IBM z13i processor chip (referred to as the CP or Central Processor chip) is guided by three basic principles: (a) controlling the peak power consumption by setting a realistic limit on the so-called thermal design power or thermal design point (TDP) driven by customer workloads and maximum-power stress microbenchmarks; (b) reduction of the voltage margin by using a novel dynamic guard-banding technique; and (c) the creation of a rich new set of fine-grained, time-synchronized sensors that track performance, power, temperature, and power management behavior for a running machine. A prime requirement of the power management architecture is that the efficient control mechanisms be designed in such a manner that the high standards of IBM z Systemsi application performance and reliability be maintained without any compromise. In this paper, we describe the key features constituting the z13 CP robust power management architecture and design that meet the stipulated objectives.

show abstract

Section: Power-management Overviewmentioning

confidence: 99%

Section: Power-management Overviewmentioning

confidence: 99%